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AlSaqr-platform

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  1. he-soc he-soc Public

    C 33 7

  2. can_bus can_bus Public

    VHDL 5 1

  3. riscv_nn riscv_nn Public

    SystemVerilog 3 2

  4. sdio_vip sdio_vip Public

    sdiovip

    Verilog 2

  5. i3c-slave-design i3c-slave-design Public

    Forked from NXP/i3c-slave-design

    MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

    Verilog 1 1

  6. pulp pulp Public

    Forked from pulp-platform/pulp

    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

    SystemVerilog

Repositories

Showing 10 of 62 repositories
  • cva6 Public Forked from openhwgroup/cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    AlSaqr-platform/cva6’s past year of commit activity
    Assembly 0 709 0 0 Updated Dec 24, 2024
  • he-soc Public
    AlSaqr-platform/he-soc’s past year of commit activity
    C 33 7 0 0 Updated Dec 23, 2024
  • cva6-sdk Public Forked from openhwgroup/cva6-sdk

    CVA6 SDK containing RISC-V tools and Buildroot

    AlSaqr-platform/cva6-sdk’s past year of commit activity
    Makefile 0 67 0 0 Updated Dec 20, 2024
  • opensbi Public Forked from riscv-software-src/opensbi

    RISC-V Open Source Supervisor Binary Interface

    AlSaqr-platform/opensbi’s past year of commit activity
    C 0 531 0 0 Updated Dec 20, 2024
  • riscv_nn Public
    AlSaqr-platform/riscv_nn’s past year of commit activity
    SystemVerilog 3 2 0 0 Updated Dec 18, 2024
  • hyper_bus Public
    AlSaqr-platform/hyper_bus’s past year of commit activity
    VHDL 0 0 0 0 Updated Dec 10, 2024
  • opentitan Public Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    AlSaqr-platform/opentitan’s past year of commit activity
    SystemVerilog 0 Apache-2.0 805 0 1 Updated Nov 27, 2024
  • pulp_cluster Public Forked from pulp-platform/pulp_cluster

    The multi-core cluster of a PULP system.

    AlSaqr-platform/pulp_cluster’s past year of commit activity
    SystemVerilog 0 22 0 1 Updated Nov 12, 2024
  • AlSaqr-platform/hier-icache’s past year of commit activity
    SystemVerilog 0 10 0 0 Updated Nov 12, 2024
  • ibex Public Forked from Arshaan-256/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    AlSaqr-platform/ibex’s past year of commit activity
    SystemVerilog 0 Apache-2.0 557 0 0 Updated Nov 5, 2024

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