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    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      Other
      705000Updated Dec 24, 2024Dec 24, 2024
    • he-soc

      Public
      C
      Other
      73300Updated Dec 23, 2024Dec 23, 2024
    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      67000Updated Dec 20, 2024Dec 20, 2024
    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      Other
      522000Updated Dec 20, 2024Dec 20, 2024
    • riscv_nn

      Public
      SystemVerilog
      Other
      2300Updated Dec 18, 2024Dec 18, 2024
    • hyper_bus

      Public
      VHDL
      0000Updated Dec 10, 2024Dec 10, 2024
    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      Apache License 2.0
      792001Updated Nov 27, 2024Nov 27, 2024
    • The multi-core cluster of a PULP system.
      SystemVerilog
      Other
      21001Updated Nov 12, 2024Nov 12, 2024
    • SystemVerilog
      Other
      10000Updated Nov 12, 2024Nov 12, 2024
    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      SystemVerilog
      Apache License 2.0
      554000Updated Nov 5, 2024Nov 5, 2024
    • axi_llc

      Public
      SystemVerilog
      Other
      15000Updated Oct 24, 2024Oct 24, 2024
    • riscv-aia

      Public
      AIA IP compliant with the RISC-V AIA spec
      SystemVerilog
      Apache License 2.0
      7000Updated Oct 15, 2024Oct 15, 2024
    • IOPMP IP
      SystemVerilog
      Apache License 2.0
      2001Updated Oct 15, 2024Oct 15, 2024
    • IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
      SystemVerilog
      Apache License 2.0
      17000Updated Oct 15, 2024Oct 15, 2024
    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      Other
      29000Updated Sep 27, 2024Sep 27, 2024
    • SystemVerilog
      Other
      6000Updated Jul 26, 2024Jul 26, 2024
    • Splash-3

      Public
      The Splash-3 benchmark suite
      GLSL
      27000Updated Jul 16, 2024Jul 16, 2024
    • A tool to run litmus tests on bare-metal hardware
      C
      Other
      12000Updated Jun 10, 2024Jun 10, 2024
    • HTML
      Other
      0000Updated May 29, 2024May 29, 2024
    • culsans

      Public
      Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
      C
      11000Updated May 22, 2024May 22, 2024
    • ace

      Public
      SystemVerilog
      4000Updated Apr 26, 2024Apr 26, 2024
    • ethernet

      Public
      Ethernet for Al Saqr platform
      SystemVerilog
      MIT License
      0000Updated Apr 16, 2024Apr 16, 2024
    • padrick

      Public
      Padrick - A Smart Pad-Multiplexer IP Generator for SoCs
      Python
      Apache License 2.0
      3001Updated Mar 13, 2024Mar 13, 2024
    • Advanced timer with APB interface
      SystemVerilog
      Other
      7000Updated Mar 11, 2024Mar 11, 2024
    • openpiton

      Public
      The OpenPiton Platform
      Assembly
      218000Updated Feb 28, 2024Feb 28, 2024
    • AXI Adapter(s) for RISC-V Atomic Operations
      SystemVerilog
      Other
      15000Updated Feb 16, 2024Feb 16, 2024
    • Simple runtime for Pulp platforms
      C
      34000Updated Jan 19, 2024Jan 19, 2024
    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      Other
      272000Updated Oct 11, 2023Oct 11, 2023
    • sdio_vip

      Public
      sdiovip
      Verilog
      0200Updated Sep 15, 2023Sep 15, 2023
    • can_bus

      Public
      VHDL
      Other
      1500Updated Aug 10, 2023Aug 10, 2023