Circuit Synthesis for Yao's Garbled Circuit by TinyGarble

This is the standalone circuit synthesis library of TinyGarble [1]. Besides the TinyGarble framework, currently, it supports the EMP Toolkit [2] and Semi-Honest-BMR [3].

Steps:

1. Write a Verilog file (.v) describing the function. You can utilize the free-XOR optimized implementations of common arithmetic and logical operations provided in the syn_lib.
2. Write a wrapper according to the template provided inside Verilog2SCD, Verilog2EMP or Verilog2BMR for executing with TinyGarble, EMP Toolkit, and Semi-Honest-BMR respectively.
3. Synthesize the Verilog file using TinyGarble's Synthesis Library to generate a netlist Verilog file (.v). It supports synthesis with Synopsys Design Compiler or Yosys-ABC.
4. Translate the netlist file (.v) to a circuit description file compatible with the respective framework following the instructions inside Verilog2SCD, Verilog2EMP or Verilog2BMR for executing with TinyGarble, EMP Toolkit, and Semi-Honest-BMR respectively.
5. Execute the respective framework with the compiled circuit description file.

Detailed instruction for each step is provided inside the respective directories.

The Benchmarks directory contains implementations of benchmark functions for 2-party GC. For multi-party benchmarks visit here.

References

[1] Ebrahim M. Songhori, Siam U. Hussain, Ahmad-Reza Sadeghi, Thomas Schneider and Farinaz Koushanfar, "TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits." Security and Privacy, 2015 IEEE Symposium on May, 2015.

[2] Xiao Wang and Alex J. Malozemoff and Jonathan Katz. "EMP-toolkit: Efficient MultiParty computation toolkit.", 2016.

[3] Ben-Efraim, Aner, Yehuda Lindell, and Eran Omri. "Optimizing semi-honest secure multiparty computation for the internet." Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security. ACM, 2016.