constant integration updates

.travis.yml

@@ -31,8 +31,9 @@ script:
   - ci/blackbox.sh -run_2c
   - ci/blackbox.sh -run_4c
   - ci/blackbox.sh -run_4c_l2
-  - ci/blackbox.sh -run_8c_2l2
-  - ci/blackbox.sh -run_16c_4l2_l3
+  #- travis_wait 30 ci/blackbox.sh -run_8c_2l2
+  #- travis_wait 30 ci/blackbox.sh -run_4c_2l2_l3
+  #- travis_wait 30 ci/blackbox.sh -run_8c_4l2_l3
 
 after_success:
   # Gather code coverage

ci/blackbox.sh

@@ -1,5 +1,8 @@
 #!/bin/sh
 
+# exit when any command fails
+set -e
+
 run_1c()
 {
     # test single core

ci/prebuilt.sh

@@ -1,5 +1,8 @@
 #!/bin/bash
 
+# exit when any command fails
+set -e
+
 OS_DIR=ubuntu/bionic
 SRCDIR=/opt
 DESTDIR=.

ci/test_driver.sh

@@ -1,3 +1,6 @@
 #!/bin/bash
 
+# exit when any command fails
+set -e
+
 make -C driver/tests run

ci/test_opencl.sh

@@ -1,3 +1,6 @@
 #!/bin/sh
 
+# exit when any command fails
+set -e
+
 make -C benchmarks/opencl run

ci/test_riscv_isa.sh

@@ -1,3 +1,6 @@
 #!/bin/bash
 
+# exit when any command fails
+set -e
+
 make -C hw/simulate run

ci/test_runtime.sh

@@ -1,3 +1,6 @@
 #!/bin/bash
 
+# exit when any command fails
+set -e
+
 make -C runtime/tests run

ci/toolchain_install.sh

@@ -1,5 +1,8 @@
 #!/bin/bash
 
+# exit when any command fails
+set -e
+
 REPOSITORY=https://github.com/vortexgpgpu/vortex-toolchain-prebuilt/raw/master
 
 riscv()

driver/opae/vlsim/Makefile

@@ -20,7 +20,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
 DBG_FLAGS += $(DBG_PRINT_FLAGS)
 DBG_FLAGS += -DDBG_CACHE_REQ_INFO
 
-#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1 
+#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1
 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
 CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1

driver/rtlsim/Makefile

@@ -20,7 +20,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
 DBG_FLAGS += $(DBG_PRINT_FLAGS)
 DBG_FLAGS += -DDBG_CACHE_REQ_INFO
 
-#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
+#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1
 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
 CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1

hw/rtl/cache/VX_bank.v

@@ -860,8 +860,8 @@ module VX_bank #(
 
 `ifdef DBG_PRINT_CACHE_BANK
     always @(posedge clk) begin        
-        if (miss_st3 && (incoming_st0_fill_st3 || incoming_st1_fill_st3 || incoming_st2_fill_st3)) begin
-            $display("%t: incoming fill - addr=%0h, st0=%b, st1=%b, st2=%b", $time, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), incoming_st0_fill_st3, incoming_st1_fill_st3, incoming_st2_fill_st3);
+        if (miss_st3 && incoming_fill) begin
+            $display("%t: incoming fill - addr=%0h, st3=%b, dfp=%b", $time, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), incoming_fill_st3, incoming_fill_dfp_st3);
             assert(!is_msrq_st3);
         end
         if (pipeline_stall) begin