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dialects: (stream) remove stream dialect and move types to memref_stream and snitch #3510

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Nov 25, 2024
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dialects: (stream) remove stream dialect and move types to memref_stream and snitch #3510

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4 changes: 2 additions & 2 deletions tests/filecheck/backend/riscv/convert_riscv_scf_for_to_frep.mlir
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Expand Up @@ -7,8 +7,8 @@
%c1 = riscv.li 1 : !riscv.reg
%c2 = riscv.li 2 : !riscv.reg

%readable = riscv_snitch.get_stream : !stream.readable<!riscv.freg<ft0>>
%writable = riscv_snitch.get_stream : !stream.writable<!riscv.freg<ft1>>
%readable = riscv_snitch.get_stream : !snitch.readable<!riscv.freg<ft0>>
%writable = riscv_snitch.get_stream : !snitch.writable<!riscv.freg<ft1>>

%f0 = riscv.get_float_register : !riscv.freg<ft2>
%f1 = riscv.get_float_register : !riscv.freg<ft3>
Expand Down
12 changes: 6 additions & 6 deletions tests/filecheck/backend/riscv/register-allocation/exclude_snitch.mlir
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Expand Up @@ -2,7 +2,7 @@
// RUN: xdsl-opt --split-input-file -p "riscv-allocate-registers{allocation_strategy=LivenessBlockNaive exclude_snitch_reserved=false}" %s | filecheck %s --check-prefix=CHECK-SNITCH-UNRESERVED

riscv_func.func @main() {
%stream = "test.op"() : () -> (!stream.readable<!riscv.freg<ft0>>)
%stream = "test.op"() : () -> (!snitch.readable<!riscv.freg<ft0>>)
%v0, %v1, %v2 = "test.op"() : () -> (!riscv.freg, !riscv.freg, !riscv.freg)
%read = riscv_snitch.read from %stream : !riscv.freg<ft0>
%sum1 = riscv.fadd.s %v0, %v1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
Expand All @@ -11,7 +11,7 @@ riscv_func.func @main() {

// CHECK: builtin.module {
// CHECK-NEXT: riscv_func.func @main() {
// CHECK-NEXT: %stream = "test.op"() : () -> !stream.readable<!riscv.freg<ft0>>
// CHECK-NEXT: %stream = "test.op"() : () -> !snitch.readable<!riscv.freg<ft0>>
// CHECK-NEXT: %v0, %v1, %v2 = "test.op"() : () -> (!riscv.freg<ft3>, !riscv.freg<ft4>, !riscv.freg)
// CHECK-NEXT: %read = riscv_snitch.read from %stream : !riscv.freg<ft0>
// CHECK-NEXT: %sum1 = riscv.fadd.s %v0, %v1 : (!riscv.freg<ft3>, !riscv.freg<ft4>) -> !riscv.freg<ft3>
Expand All @@ -21,7 +21,7 @@ riscv_func.func @main() {

// CHECK-SNITCH-UNRESERVED: builtin.module {
// CHECK-SNITCH-UNRESERVED-NEXT: riscv_func.func @main() {
// CHECK-SNITCH-UNRESERVED-NEXT: %stream = "test.op"() : () -> !stream.readable<!riscv.freg<ft0>>
// CHECK-SNITCH-UNRESERVED-NEXT: %stream = "test.op"() : () -> !snitch.readable<!riscv.freg<ft0>>
// CHECK-SNITCH-UNRESERVED-NEXT: %v0, %v1, %v2 = "test.op"() : () -> (!riscv.freg<ft1>, !riscv.freg<ft2>, !riscv.freg)
// CHECK-SNITCH-UNRESERVED-NEXT: %read = riscv_snitch.read from %stream : !riscv.freg<ft0>
// CHECK-SNITCH-UNRESERVED-NEXT: %sum1 = riscv.fadd.s %v0, %v1 : (!riscv.freg<ft1>, !riscv.freg<ft2>) -> !riscv.freg<ft1>
Expand All @@ -32,7 +32,7 @@ riscv_func.func @main() {
// -----

riscv_func.func @main() {
%stream, %val = "test.op"() : () -> (!stream.writable<!riscv.freg<ft0>>, !riscv.freg<ft0>)
%stream, %val = "test.op"() : () -> (!snitch.writable<!riscv.freg<ft0>>, !riscv.freg<ft0>)
%v0, %v1, %v2 = "test.op"() : () -> (!riscv.freg, !riscv.freg, !riscv.freg)
riscv_snitch.write %val to %stream : !riscv.freg<ft0>
%sum1 = riscv.fadd.s %v0, %v1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
Expand All @@ -41,7 +41,7 @@ riscv_func.func @main() {

// CHECK: builtin.module {
// CHECK-NEXT: riscv_func.func @main() {
// CHECK-NEXT: %stream, %val = "test.op"() : () -> (!stream.writable<!riscv.freg<ft0>>, !riscv.freg<ft0>)
// CHECK-NEXT: %stream, %val = "test.op"() : () -> (!snitch.writable<!riscv.freg<ft0>>, !riscv.freg<ft0>)
// CHECK-NEXT: %v0, %v1, %v2 = "test.op"() : () -> (!riscv.freg<ft3>, !riscv.freg<ft4>, !riscv.freg)
// CHECK-NEXT: riscv_snitch.write %val to %stream : !riscv.freg<ft0>
// CHECK-NEXT: %sum1 = riscv.fadd.s %v0, %v1 : (!riscv.freg<ft3>, !riscv.freg<ft4>) -> !riscv.freg<ft3>
Expand All @@ -51,7 +51,7 @@ riscv_func.func @main() {

// CHECK-SNITCH-UNRESERVED: builtin.module {
// CHECK-SNITCH-UNRESERVED-NEXT: riscv_func.func @main() {
// CHECK-SNITCH-UNRESERVED-NEXT: %stream, %val = "test.op"() : () -> (!stream.writable<!riscv.freg<ft0>>, !riscv.freg<ft0>)
// CHECK-SNITCH-UNRESERVED-NEXT: %stream, %val = "test.op"() : () -> (!snitch.writable<!riscv.freg<ft0>>, !riscv.freg<ft0>)
// CHECK-SNITCH-UNRESERVED-NEXT: %v0, %v1, %v2 = "test.op"() : () -> (!riscv.freg<ft1>, !riscv.freg<ft2>, !riscv.freg)
// CHECK-SNITCH-UNRESERVED-NEXT: riscv_snitch.write %val to %stream : !riscv.freg<ft0>
// CHECK-SNITCH-UNRESERVED-NEXT: %sum1 = riscv.fadd.s %v0, %v1 : (!riscv.freg<ft1>, !riscv.freg<ft2>) -> !riscv.freg<ft1>
Expand Down
22 changes: 11 additions & 11 deletions tests/filecheck/dialects/memref_stream/ops.mlir
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Expand Up @@ -4,18 +4,18 @@
// CHECK:builtin.module {
// CHECK-GENERIC: "builtin.module"() ({

%readable, %writable = "test.op"() : () -> (!stream.readable<f32>, !stream.writable<f32>)
%readable, %writable = "test.op"() : () -> (!memref_stream.readable<f32>, !memref_stream.writable<f32>)

%val = memref_stream.read from %readable : f32
memref_stream.write %val to %writable : f32

// CHECK-NEXT: %readable, %writable = "test.op"() : () -> (!stream.readable<f32>, !stream.writable<f32>)
// CHECK-NEXT: %readable, %writable = "test.op"() : () -> (!memref_stream.readable<f32>, !memref_stream.writable<f32>)
// CHECK-NEXT: %val = memref_stream.read from %readable : f32
// CHECK-NEXT: memref_stream.write %val to %writable : f32

// CHECK-GENERIC-NEXT: %readable, %writable = "test.op"() : () -> (!stream.readable<f32>, !stream.writable<f32>)
// CHECK-GENERIC-NEXT: %val = "memref_stream.read"(%readable) : (!stream.readable<f32>) -> f32
// CHECK-GENERIC-NEXT: "memref_stream.write"(%val, %writable) : (f32, !stream.writable<f32>) -> ()
// CHECK-GENERIC-NEXT: %readable, %writable = "test.op"() : () -> (!memref_stream.readable<f32>, !memref_stream.writable<f32>)
// CHECK-GENERIC-NEXT: %val = "memref_stream.read"(%readable) : (!memref_stream.readable<f32>) -> f32
// CHECK-GENERIC-NEXT: "memref_stream.write"(%val, %writable) : (f32, !memref_stream.writable<f32>) -> ()

%A, %B, %C, %D = "test.op"() : () -> (memref<2xf32>, memref<3xf32>, memref<3x2xf64>, f64)

Expand All @@ -26,8 +26,8 @@ memref_stream.streaming_region {
#memref_stream.stride_pattern<ub = [3, 2], index_map = (d0, d1) -> (d0, d1)>
]
} ins(%A, %B : memref<2xf32>, memref<3xf32>) outs(%C : memref<3x2xf64>) attrs = {hello = "world"} {
^bb0(%a: !stream.readable<f32>, %b: !stream.readable<f32>, %c: !stream.writable<f64>):
"test.op"(%a, %b, %c) : (!stream.readable<f32>, !stream.readable<f32>, !stream.writable<f64>) -> ()
^bb0(%a: !memref_stream.readable<f32>, %b: !memref_stream.readable<f32>, %c: !memref_stream.writable<f64>):
"test.op"(%a, %b, %c) : (!memref_stream.readable<f32>, !memref_stream.readable<f32>, !memref_stream.writable<f64>) -> ()
}

// CHECK-NEXT: %A, %B, %C, %D = "test.op"() : () -> (memref<2xf32>, memref<3xf32>, memref<3x2xf64>, f64)
Expand All @@ -38,14 +38,14 @@ memref_stream.streaming_region {
// CHECK-NEXT: #memref_stream.stride_pattern<ub = [3, 2], index_map = (d0, d1) -> (d0, d1)>
// CHECK-NEXT: ]
// CHECK-NEXT: } ins(%A, %B : memref<2xf32>, memref<3xf32>) outs(%C : memref<3x2xf64>) attrs = {"hello" = "world"} {
// CHECK-NEXT: ^0(%a : !stream.readable<f32>, %b : !stream.readable<f32>, %c : !stream.writable<f64>):
// CHECK-NEXT: "test.op"(%a, %b, %c) : (!stream.readable<f32>, !stream.readable<f32>, !stream.writable<f64>) -> ()
// CHECK-NEXT: ^0(%a : !memref_stream.readable<f32>, %b : !memref_stream.readable<f32>, %c : !memref_stream.writable<f64>):
// CHECK-NEXT: "test.op"(%a, %b, %c) : (!memref_stream.readable<f32>, !memref_stream.readable<f32>, !memref_stream.writable<f64>) -> ()
// CHECK-NEXT: }

// CHECK-GENERIC-NEXT: %A, %B, %C, %D = "test.op"() : () -> (memref<2xf32>, memref<3xf32>, memref<3x2xf64>, f64)
// CHECK-GENERIC-NEXT: "memref_stream.streaming_region"(%A, %B, %C) <{"patterns" = [#memref_stream.stride_pattern<ub = [3, 2], index_map = (d0, d1) -> (d0)>, #memref_stream.stride_pattern<ub = [3, 2], index_map = (d0, d1) -> (d1)>, #memref_stream.stride_pattern<ub = [3, 2], index_map = (d0, d1) -> (d0, d1)>], "operandSegmentSizes" = array<i32: 2, 1>}> ({
// CHECK-GENERIC-NEXT: ^0(%a : !stream.readable<f32>, %b : !stream.readable<f32>, %c : !stream.writable<f64>):
// CHECK-GENERIC-NEXT: "test.op"(%a, %b, %c) : (!stream.readable<f32>, !stream.readable<f32>, !stream.writable<f64>) -> ()
// CHECK-GENERIC-NEXT: ^0(%a : !memref_stream.readable<f32>, %b : !memref_stream.readable<f32>, %c : !memref_stream.writable<f64>):
// CHECK-GENERIC-NEXT: "test.op"(%a, %b, %c) : (!memref_stream.readable<f32>, !memref_stream.readable<f32>, !memref_stream.writable<f64>) -> ()
// CHECK-GENERIC-NEXT: }) {"hello" = "world"} : (memref<2xf32>, memref<3xf32>, memref<3x2xf64>) -> ()


Expand Down
4 changes: 2 additions & 2 deletions tests/filecheck/dialects/riscv_snitch/assembly_emission.mlir
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Expand Up @@ -5,8 +5,8 @@ riscv_func.func @main() {
%0 = riscv.get_register : !riscv.reg<a0>
%1 = riscv.get_register : !riscv.reg<a1>

%readable = riscv_snitch.get_stream : !stream.readable<!riscv.freg<ft0>>
%writable = riscv_snitch.get_stream : !stream.writable<!riscv.freg<ft1>>
%readable = riscv_snitch.get_stream : !snitch.readable<!riscv.freg<ft0>>
%writable = riscv_snitch.get_stream : !snitch.writable<!riscv.freg<ft1>>
riscv_snitch.frep_outer %0 {
%val0 = riscv_snitch.read from %readable : !riscv.freg<ft0>
%val1 = riscv.fmv.d %val0 : (!riscv.freg<ft0>) -> !riscv.freg<ft1>
Expand Down
16 changes: 8 additions & 8 deletions tests/filecheck/dialects/riscv_snitch/ops.mlir
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Expand Up @@ -25,15 +25,15 @@ riscv_func.func @xfrep() {
// CHECK-NEXT: %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
// CHECK-NEXT: }

%readable = riscv_snitch.get_stream : !stream.readable<!riscv.freg<ft0>>
%writable = riscv_snitch.get_stream : !stream.writable<!riscv.freg<ft1>>
%readable = riscv_snitch.get_stream : !snitch.readable<!riscv.freg<ft0>>
%writable = riscv_snitch.get_stream : !snitch.writable<!riscv.freg<ft1>>
riscv_snitch.frep_outer %0 {
%val0 = riscv_snitch.read from %readable : !riscv.freg<ft0>
%val1 = riscv.fmv.d %val0 : (!riscv.freg<ft0>) -> !riscv.freg<ft1>
riscv_snitch.write %val1 to %writable : !riscv.freg<ft1>
}
// CHECK-NEXT: %readable = riscv_snitch.get_stream : !stream.readable<!riscv.freg<ft0>>
// CHECK-NEXT: %writable = riscv_snitch.get_stream : !stream.writable<!riscv.freg<ft1>>
// CHECK-NEXT: %readable = riscv_snitch.get_stream : !snitch.readable<!riscv.freg<ft0>>
// CHECK-NEXT: %writable = riscv_snitch.get_stream : !snitch.writable<!riscv.freg<ft1>>
// CHECK-NEXT: riscv_snitch.frep_outer %0 {
// CHECK-NEXT: %val0 = riscv_snitch.read from %readable : !riscv.freg<ft0>
// CHECK-NEXT: %val1 = riscv.fmv.d %val0 : (!riscv.freg<ft0>) -> !riscv.freg<ft1>
Expand Down Expand Up @@ -129,12 +129,12 @@ riscv_func.func @simd() {
// CHECK-GENERIC-NEXT: %{{.*}} = "riscv.add"(%{{.*}}, %{{.*}}) : (!riscv.reg, !riscv.reg) -> !riscv.reg
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_yield"() : () -> ()
// CHECK-GENERIC-NEXT: }) {"stagger_mask" = #builtin.int<0>, "stagger_count" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK-GENERIC-NEXT: %readable = "riscv_snitch.get_stream"() : () -> !stream.readable<!riscv.freg<ft0>>
// CHECK-GENERIC-NEXT: %writable = "riscv_snitch.get_stream"() : () -> !stream.writable<!riscv.freg<ft1>>
// CHECK-GENERIC-NEXT: %readable = "riscv_snitch.get_stream"() : () -> !snitch.readable<!riscv.freg<ft0>>
// CHECK-GENERIC-NEXT: %writable = "riscv_snitch.get_stream"() : () -> !snitch.writable<!riscv.freg<ft1>>
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_outer"(%0) ({
// CHECK-GENERIC-NEXT: %val0 = "riscv_snitch.read"(%readable) : (!stream.readable<!riscv.freg<ft0>>) -> !riscv.freg<ft0>
// CHECK-GENERIC-NEXT: %val0 = "riscv_snitch.read"(%readable) : (!snitch.readable<!riscv.freg<ft0>>) -> !riscv.freg<ft0>
// CHECK-GENERIC-NEXT: %val1 = "riscv.fmv.d"(%val0) : (!riscv.freg<ft0>) -> !riscv.freg<ft1>
// CHECK-GENERIC-NEXT: "riscv_snitch.write"(%val1, %writable) : (!riscv.freg<ft1>, !stream.writable<!riscv.freg<ft1>>) -> ()
// CHECK-GENERIC-NEXT: "riscv_snitch.write"(%val1, %writable) : (!riscv.freg<ft1>, !snitch.writable<!riscv.freg<ft1>>) -> ()
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_yield"() : () -> ()
// CHECK-GENERIC-NEXT: }) {"stagger_mask" = #builtin.int<0>, "stagger_count" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK-GENERIC-NEXT: %init = "test.op"() : () -> !riscv.freg<ft3>
Expand Down
8 changes: 4 additions & 4 deletions tests/filecheck/dialects/snitch_stream/convert_snitch_stream_to_snitch.mlir
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Expand Up @@ -13,7 +13,7 @@
],
"operandSegmentSizes" = array<i32: 2, 1>
}> ({
^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.readable<!riscv.freg<ft1>>, %c_stream : !stream.writable<!riscv.freg<ft2>>):
^0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
"test.op"() : () -> ()
}) : (!riscv.reg, !riscv.reg, !riscv.reg) -> ()
// CHECK-NEXT: %{{.*}} = riscv.li 2 : !riscv.reg
Expand Down Expand Up @@ -75,7 +75,7 @@
// CHECK-NEXT: "snitch.ssr_set_dimension_source"(%A) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK-NEXT: "snitch.ssr_set_dimension_source"(%B) {"dm" = #builtin.int<1>, "dimension" = #builtin.int<1>} : (!riscv.reg) -> ()
// CHECK-NEXT: "snitch.ssr_set_dimension_destination"(%C) {"dm" = #builtin.int<2>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
// CHECK-NEXT: %a_stream, %b_stream, %c_stream = "snitch.ssr_enable"() : () -> (!stream.readable<!riscv.freg<ft0>>, !stream.readable<!riscv.freg<ft1>>, !stream.writable<!riscv.freg<ft2>>)
// CHECK-NEXT: %a_stream, %b_stream, %c_stream = "snitch.ssr_enable"() : () -> (!snitch.readable<!riscv.freg<ft0>>, !snitch.readable<!riscv.freg<ft1>>, !snitch.writable<!riscv.freg<ft2>>)
// CHECK-NEXT: "test.op"() : () -> ()
// CHECK-NEXT: "snitch.ssr_disable"() : () -> ()

Expand All @@ -85,7 +85,7 @@
],
"operandSegmentSizes" = array<i32: 1, 1>
}> ({
^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.writable<!riscv.freg<ft1>>):
^0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.writable<!riscv.freg<ft1>>):
"test.op"() : () -> ()
}) : (!riscv.reg, !riscv.reg) -> ()

Expand All @@ -99,7 +99,7 @@
// CHECK-NEXT: "snitch.ssr_set_stream_repetition"(%{{.*}}) {"dm" = #builtin.int<31>} : (!riscv.reg) -> ()
// CHECK-NEXT: "snitch.ssr_set_dimension_source"(%A) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK-NEXT: "snitch.ssr_set_dimension_destination"(%B) {"dm" = #builtin.int<1>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK-NEXT: %{{.*}}, %{{.*}} = "snitch.ssr_enable"() : () -> (!stream.readable<!riscv.freg<ft0>>, !stream.writable<!riscv.freg<ft1>>)
// CHECK-NEXT: %{{.*}}, %{{.*}} = "snitch.ssr_enable"() : () -> (!snitch.readable<!riscv.freg<ft0>>, !snitch.writable<!riscv.freg<ft1>>)
// CHECK-NEXT: "test.op"() : () -> ()
// CHECK-NEXT: "snitch.ssr_disable"() : () -> ()

Expand Down
12 changes: 6 additions & 6 deletions tests/filecheck/dialects/snitch_stream/ops.mlir
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Expand Up @@ -8,7 +8,7 @@ snitch_stream.streaming_region {
#snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>
]
} ins(%X, %Y : !riscv.reg, !riscv.reg) outs(%Z : !riscv.reg) {
^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.readable<!riscv.freg<ft1>>, %c_stream : !stream.writable<!riscv.freg<ft2>>):
^0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
%c5 = riscv.li 5 : !riscv.reg
riscv_snitch.frep_outer %c5 {
%a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
Expand All @@ -26,7 +26,7 @@ snitch_stream.streaming_region {
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>
// CHECK-NEXT: ]
// CHECK-NEXT: } ins(%X, %Y : !riscv.reg, !riscv.reg) outs(%Z : !riscv.reg) {
// CHECK-NEXT: ^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.readable<!riscv.freg<ft1>>, %c_stream : !stream.writable<!riscv.freg<ft2>>):
// CHECK-NEXT: ^0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
// CHECK-NEXT: %c5 = riscv.li 5 : !riscv.reg
// CHECK-NEXT: riscv_snitch.frep_outer %c5 {
// CHECK-NEXT: %a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
Expand All @@ -38,13 +38,13 @@ snitch_stream.streaming_region {

// CHECK-GENERIC: %X, %Y, %Z = "test.op"() : () -> (!riscv.reg, !riscv.reg, !riscv.reg)
// CHECK-GENERIC-NEXT: "snitch_stream.streaming_region"(%X, %Y, %Z) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>], "operandSegmentSizes" = array<i32: 2, 1>}> ({
// CHECK-GENERIC-NEXT: ^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.readable<!riscv.freg<ft1>>, %c_stream : !stream.writable<!riscv.freg<ft2>>):
// CHECK-GENERIC-NEXT: ^0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
// CHECK-GENERIC-NEXT: %c5 = "riscv.li"() {"immediate" = 5 : i32} : () -> !riscv.reg
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_outer"(%c5) ({
// CHECK-GENERIC-NEXT: %a = "riscv_snitch.read"(%a_stream) : (!stream.readable<!riscv.freg<ft0>>) -> !riscv.freg<ft0>
// CHECK-GENERIC-NEXT: %b = "riscv_snitch.read"(%b_stream) : (!stream.readable<!riscv.freg<ft1>>) -> !riscv.freg<ft1>
// CHECK-GENERIC-NEXT: %a = "riscv_snitch.read"(%a_stream) : (!snitch.readable<!riscv.freg<ft0>>) -> !riscv.freg<ft0>
// CHECK-GENERIC-NEXT: %b = "riscv_snitch.read"(%b_stream) : (!snitch.readable<!riscv.freg<ft1>>) -> !riscv.freg<ft1>
// CHECK-GENERIC-NEXT: %c = "riscv.fadd.d"(%a, %b) {"fastmath" = #riscv.fastmath<none>} : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft2>
// CHECK-GENERIC-NEXT: "riscv_snitch.write"(%c, %c_stream) : (!riscv.freg<ft2>, !stream.writable<!riscv.freg<ft2>>) -> ()
// CHECK-GENERIC-NEXT: "riscv_snitch.write"(%c, %c_stream) : (!riscv.freg<ft2>, !snitch.writable<!riscv.freg<ft2>>) -> ()
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_yield"() : () -> ()
// CHECK-GENERIC-NEXT: }) {"stagger_mask" = #builtin.int<0>, "stagger_count" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK-GENERIC-NEXT: }) : (!riscv.reg, !riscv.reg, !riscv.reg) -> ()
2 changes: 1 addition & 1 deletion tests/filecheck/projects/riscv-backend-paper/add_snitch_stream.mlir
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Expand Up @@ -20,7 +20,7 @@ builtin.module {
"stride_patterns" = [#snitch_stream.stride_pattern<ub = [2, 3], strides = [24, 8]>],
"operandSegmentSizes" = array<i32: 2, 1>
}> ({
^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.readable<!riscv.freg<ft1>>, %c_stream : !stream.writable<!riscv.freg<ft2>>):
^0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
%c5 = riscv.li 5 : !riscv.reg
riscv_snitch.frep_outer %c5 {
%a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
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4 changes: 2 additions & 2 deletions tests/filecheck/projects/riscv-backend-paper/bottom_up.mlir
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Expand Up @@ -181,7 +181,7 @@ func.func public @conv_2d_nchw_fchw_d1_s1_3x3(
#memref_stream.stride_pattern<ub = [128], index_map = (d0) -> (d0)>
]
} ins(%X, %Y : memref<128xf64>, memref<128xf64>) {
^0(%x_stream : !stream.readable<f64>, %y_stream : !stream.readable<f64>):
^0(%x_stream : !memref_stream.readable<f64>, %y_stream : !memref_stream.readable<f64>):
%zero_float = arith.constant 0.0 : f64

%c0 = arith.constant 0 : i32
Expand Down Expand Up @@ -593,7 +593,7 @@ func.func public @pooling_nchw_max_d1_s2_3x3(
#snitch_stream.stride_pattern<ub = [128], strides = [8]>
]
} ins(%X_1 : !riscv.reg) outs(%Y_1 : !riscv.reg) {
^0(%x : !stream.readable<!riscv.freg<ft0>>, %0 : !stream.writable<!riscv.freg<ft1>>):
^0(%x : !snitch.readable<!riscv.freg<ft0>>, %0 : !snitch.writable<!riscv.freg<ft1>>):
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@alexarice alexarice Nov 25, 2024 •
edited
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What was the decision process for when to use snitch and when to use memref_stream? This file for example uses both.

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wdym? this file was used to go from snitch/risc-v all the way up to linalg when modelling the lowering for the other way around.

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This is probably just me not knowing much about this side of xDSL, but in this PR some cases of !stream.(readable|writable) are changed to !memref_stream.... and some are changed to !snitch.... and I couldn't really see a pattern. As a result I feel I can't really review this at the moment (though I wasn't pinged for a review (maybe for this reason)).

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it's entirely determined by the operation enclosing the block in question. In this case it's a snitch_stream.streaming region, in others it's memref_stream.streaming region.

%c128 = riscv.li 128 : !riscv.reg
%c0 = riscv.li 0 : !riscv.reg
%c1 = riscv.li 1 : !riscv.reg
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2 changes: 1 addition & 1 deletion tests/filecheck/projects/riscv-backend-paper/relu_snitch_stream.mlir
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Expand Up @@ -25,7 +25,7 @@ builtin.module {
"stride_patterns" = [#snitch_stream.stride_pattern<ub = [2, 3], strides = [24, 8]>],
"operandSegmentSizes" = array<i32: 1, 1>
}> ({
^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.writable<!riscv.freg<ft1>>):
^0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.writable<!riscv.freg<ft1>>):
%c5 = riscv.li 5 : !riscv.reg
riscv_snitch.frep_outer %c5 {
%a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
Expand Down
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