Skip to content

Commit

Permalink
incorporate feedback
Browse files Browse the repository at this point in the history
  • Loading branch information
@AntonLydike
AntonLydike committed Jul 18, 2024
1 parent c82d335 commit 7fe434c
Show file tree
Hide file tree
Showing 2 changed files with 24 additions and 24 deletions.
36 changes: 18 additions & 18 deletions tests/filecheck/transforms/convert_riscv_to_llvm.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,13 +16,13 @@
%2 = riscv.sub %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
// CHECK-NEXT: %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: %4 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: %5 = "llvm.inline_asm"(%3, %4) <{"asm_string" = "sub $0, $1, $2", "constraints" = "=r,r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// CHECK-NEXT: %5 = "llvm.inline_asm"(%3, %4) <{"asm_string" = "sub $0, $1, $2", "constraints" = "=r,rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// CHECK-NEXT: %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg

%3 = riscv.div %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
// CHECK-NEXT: %7 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: %8 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: %9 = "llvm.inline_asm"(%7, %8) <{"asm_string" = "div $0, $1, $2", "constraints" = "=r,r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// CHECK-NEXT: %9 = "llvm.inline_asm"(%7, %8) <{"asm_string" = "div $0, $1, $2", "constraints" = "=r,rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// CHECK-NEXT: %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg


Expand All @@ -35,13 +35,13 @@
%5 = riscv.sub %4, %4 : (!riscv.reg<a0>, !riscv.reg<a0>) -> !riscv.reg
// CHECK-NEXT: %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg<a0> to i32
// CHECK-NEXT: %14 = builtin.unrealized_conversion_cast %12 : !riscv.reg<a0> to i32
// CHECK-NEXT: %15 = "llvm.inline_asm"(%13, %14) <{"asm_string" = "sub $0, $1, $2", "constraints" = "=r,r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// CHECK-NEXT: %15 = "llvm.inline_asm"(%13, %14) <{"asm_string" = "sub $0, $1, $2", "constraints" = "=r,rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// CHECK-NEXT: %16 = builtin.unrealized_conversion_cast %15 : i32 to !riscv.reg

%6 = riscv.div %4, %4 : (!riscv.reg<a0>, !riscv.reg<a0>) -> !riscv.reg
// CHECK-NEXT: %17 = builtin.unrealized_conversion_cast %12 : !riscv.reg<a0> to i32
// CHECK-NEXT: %18 = builtin.unrealized_conversion_cast %12 : !riscv.reg<a0> to i32
// CHECK-NEXT: %19 = "llvm.inline_asm"(%17, %18) <{"asm_string" = "div $0, $1, $2", "constraints" = "=r,r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// CHECK-NEXT: %19 = "llvm.inline_asm"(%17, %18) <{"asm_string" = "div $0, $1, $2", "constraints" = "=r,rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// CHECK-NEXT: %20 = builtin.unrealized_conversion_cast %19 : i32 to !riscv.reg


Expand All @@ -65,25 +65,25 @@
riscv_snitch.dmsrc %1, %1 : (!riscv.reg, !riscv.reg) -> ()
// CHECK-NEXT: %26 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: %27 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: "llvm.inline_asm"(%26, %27) <{"asm_string" = ".insn r 0x2b, 0, 0, x0, $0, $1", "constraints" = "r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// CHECK-NEXT: "llvm.inline_asm"(%26, %27) <{"asm_string" = ".insn r 0x2b, 0, 0, x0, $0, $1", "constraints" = "rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()

riscv_snitch.dmdst %1, %1 : (!riscv.reg, !riscv.reg) -> ()
// CHECK-NEXT: %28 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: %29 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: "llvm.inline_asm"(%28, %29) <{"asm_string" = ".insn r 0x2b, 0, 1, x0, $0, $1", "constraints" = "r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// CHECK-NEXT: "llvm.inline_asm"(%28, %29) <{"asm_string" = ".insn r 0x2b, 0, 1, x0, $0, $1", "constraints" = "rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()

riscv_snitch.dmstr %1, %1 : (!riscv.reg, !riscv.reg) -> ()
// CHECK-NEXT: %30 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: %31 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: "llvm.inline_asm"(%30, %31) <{"asm_string" = ".insn r 0x2b, 0, 6, x0, $0, $1", "constraints" = "r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// CHECK-NEXT: "llvm.inline_asm"(%30, %31) <{"asm_string" = ".insn r 0x2b, 0, 6, x0, $0, $1", "constraints" = "rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()

riscv_snitch.dmrep %1 : (!riscv.reg) -> ()
// CHECK-NEXT: %32 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: "llvm.inline_asm"(%32) <{"asm_string" = ".insn r 0x2b, 0, 7, x0, $0, x0", "constraints" = "r", "asm_dialect" = 0 : i64}> : (i32) -> ()
// CHECK-NEXT: "llvm.inline_asm"(%32) <{"asm_string" = ".insn r 0x2b, 0, 7, x0, $0, x0", "constraints" = "rI", "asm_dialect" = 0 : i64}> : (i32) -> ()

%10 = riscv_snitch.dmcpyi %1, 2 : (!riscv.reg) -> !riscv.reg
// CHECK-NEXT: %33 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32
// CHECK-NEXT: %34 = "llvm.inline_asm"(%33) <{"asm_string" = ".insn r 0x2b, 0, 2, $0, $1, 2", "constraints" = "=r,r", "asm_dialect" = 0 : i64}> : (i32) -> i32
// CHECK-NEXT: %34 = "llvm.inline_asm"(%33) <{"asm_string" = ".insn r 0x2b, 0, 2, $0, $1, 2", "constraints" = "=r,rI", "asm_dialect" = 0 : i64}> : (i32) -> i32
// CHECK-NEXT: %35 = builtin.unrealized_conversion_cast %34 : i32 to !riscv.reg


Expand All @@ -93,17 +93,17 @@ riscv_snitch.dmrep %1 : (!riscv.reg) -> ()

// COMPACT: builtin.module {
// COMPACT-NEXT: %0 = "llvm.inline_asm"() <{"asm_string" = "li $0, 0", "constraints" = "=r", "asm_dialect" = 0 : i64}> : () -> i32
// COMPACT-NEXT: %1 = "llvm.inline_asm"(%0, %0) <{"asm_string" = "sub $0, $1, $2", "constraints" = "=r,r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// COMPACT-NEXT: %2 = "llvm.inline_asm"(%0, %0) <{"asm_string" = "div $0, $1, $2", "constraints" = "=r,r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// COMPACT-NEXT: %1 = "llvm.inline_asm"(%0, %0) <{"asm_string" = "sub $0, $1, $2", "constraints" = "=r,rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// COMPACT-NEXT: %2 = "llvm.inline_asm"(%0, %0) <{"asm_string" = "div $0, $1, $2", "constraints" = "=r,rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// COMPACT-NEXT: %3 = "llvm.inline_asm"() <{"asm_string" = "li $0, 0", "constraints" = "=r", "asm_dialect" = 0 : i64}> : () -> i32
// COMPACT-NEXT: %4 = "llvm.inline_asm"(%3, %3) <{"asm_string" = "sub $0, $1, $2", "constraints" = "=r,r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// COMPACT-NEXT: %5 = "llvm.inline_asm"(%3, %3) <{"asm_string" = "div $0, $1, $2", "constraints" = "=r,r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// COMPACT-NEXT: %4 = "llvm.inline_asm"(%3, %3) <{"asm_string" = "sub $0, $1, $2", "constraints" = "=r,rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// COMPACT-NEXT: %5 = "llvm.inline_asm"(%3, %3) <{"asm_string" = "div $0, $1, $2", "constraints" = "=r,rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> i32
// COMPACT-NEXT: %6 = "llvm.inline_asm"() <{"asm_string" = "csrrs $0, 3860, x0", "constraints" = "=r", "asm_dialect" = 0 : i64}> : () -> i32
// COMPACT-NEXT: "llvm.inline_asm"() <{"asm_string" = "csrrs x0, 1986, x0", "constraints" = "", "asm_dialect" = 0 : i64}> : () -> ()
// COMPACT-NEXT: %7 = "llvm.inline_asm"() <{"asm_string" = "csrrci $0, 1984, 1", "constraints" = "=r", "asm_dialect" = 0 : i64}> : () -> i32
// COMPACT-NEXT: "llvm.inline_asm"(%0, %0) <{"asm_string" = ".insn r 0x2b, 0, 0, x0, $0, $1", "constraints" = "r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// COMPACT-NEXT: "llvm.inline_asm"(%0, %0) <{"asm_string" = ".insn r 0x2b, 0, 1, x0, $0, $1", "constraints" = "r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// COMPACT-NEXT: "llvm.inline_asm"(%0, %0) <{"asm_string" = ".insn r 0x2b, 0, 6, x0, $0, $1", "constraints" = "r,r", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// COMPACT-NEXT: "llvm.inline_asm"(%0) <{"asm_string" = ".insn r 0x2b, 0, 7, x0, $0, x0", "constraints" = "r", "asm_dialect" = 0 : i64}> : (i32) -> ()
// COMPACT-NEXT: %8 = "llvm.inline_asm"(%0) <{"asm_string" = ".insn r 0x2b, 0, 2, $0, $1, 2", "constraints" = "=r,r", "asm_dialect" = 0 : i64}> : (i32) -> i32
// COMPACT-NEXT: "llvm.inline_asm"(%0, %0) <{"asm_string" = ".insn r 0x2b, 0, 0, x0, $0, $1", "constraints" = "rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// COMPACT-NEXT: "llvm.inline_asm"(%0, %0) <{"asm_string" = ".insn r 0x2b, 0, 1, x0, $0, $1", "constraints" = "rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// COMPACT-NEXT: "llvm.inline_asm"(%0, %0) <{"asm_string" = ".insn r 0x2b, 0, 6, x0, $0, $1", "constraints" = "rI,rI", "asm_dialect" = 0 : i64}> : (i32, i32) -> ()
// COMPACT-NEXT: "llvm.inline_asm"(%0) <{"asm_string" = ".insn r 0x2b, 0, 7, x0, $0, x0", "constraints" = "rI", "asm_dialect" = 0 : i64}> : (i32) -> ()
// COMPACT-NEXT: %8 = "llvm.inline_asm"(%0) <{"asm_string" = ".insn r 0x2b, 0, 2, $0, $1, 2", "constraints" = "=r,rI", "asm_dialect" = 0 : i64}> : (i32) -> i32
// COMPACT-NEXT: }
12 changes: 6 additions & 6 deletions xdsl/transforms/convert_riscv_to_llvm.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ def match_and_rewrite(self, op: RISCVInstruction, rewriter: PatternRewriter):
conversion_op = UnrealizedConversionCastOp.get([arg], [builtin.i32])
ops_to_insert.append(conversion_op)
inputs.append(conversion_op.outputs[0])
constraints.append("r")
constraints.append("rI")
assembly_args_str.append(f"${len(inputs) + num_results - 1}")

# constant value used as an immediate
Expand All @@ -89,13 +89,13 @@ def match_and_rewrite(self, op: RISCVInstruction, rewriter: PatternRewriter):
# construct asm_string
iname = op.assembly_instruction_name()

# check if the operation has a custom insn string (for comaptibility reasons)
custom_insns = op.get_trait(HasInsnRepresentation)
if custom_insns is not None:
# check if the operation has a custom insn string (for compatibility reasons)
custom_insn = op.get_trait(HasInsnRepresentation)
if custom_insn is not None:
# generate custom insn inline assembly instruction
# tahnk you pyright for making my code so much better I truly appreciate your presence
# thank you pyright for making my code so much better I truly appreciate your presence
# put the forbidden ~fruit~ method in a variable with a short name:
n = custom_insns.get_insn
n = custom_insn.get_insn
# because if the name is too long, black will force the comment to be not in the same line as the call
# making pyright not see the comment.
# this continues to eat my sanity every day.
Expand Down

0 comments on commit 7fe434c

Please sign in to comment.