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dialects: (riscv_snitch) remove always ZERO rd in snitch config ops (#…
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…2886)

Resolves #2884
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@superlopuh
superlopuh authored Jul 15, 2024
1 parent e4ae483 commit 73c893c
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Showing 9 changed files with 95 additions and 111 deletions.
6 changes: 2 additions & 4 deletions tests/filecheck/backend/riscv/canonicalize.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -109,8 +109,7 @@ builtin.module {
"test.op"(%and_bitwise_zero_r0) : (!riscv.reg<a0>) -> ()

// scfgw immediates
%scfgw = riscv_snitch.scfgw %i1, %c1 : (!riscv.reg<a1>, !riscv.reg) -> !riscv.reg<zero>
"test.op"(%scfgw) : (!riscv.reg<zero>) -> ()
riscv_snitch.scfgw %i1, %c1 : (!riscv.reg<a1>, !riscv.reg) -> ()
}

// CHECK: builtin.module {
Expand Down Expand Up @@ -215,8 +214,7 @@ builtin.module {
// CHECK-NEXT: %and_bitwise_zero_r0 = riscv.mv %c0_1 : (!riscv.reg) -> !riscv.reg<a0>
// CHECK-NEXT: "test.op"(%and_bitwise_zero_r0) : (!riscv.reg<a0>) -> ()

// CHECK-NEXT: %scfgw = riscv_snitch.scfgwi %i1, 1 : (!riscv.reg<a1>) -> !riscv.reg<zero>
// CHECK-NEXT: "test.op"(%scfgw) : (!riscv.reg<zero>) -> ()
// CHECK-NEXT: riscv_snitch.scfgwi %i1, 1 : (!riscv.reg<a1>) -> ()

// CHECK-NEXT: }

Expand Down
31 changes: 0 additions & 31 deletions tests/filecheck/backend/riscv/verify.mlir
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Original file line number Diff line number Diff line change
@@ -1,36 +1,5 @@
// RUN: xdsl-opt --split-input-file --verify-diagnostics --parsing-diagnostics %s | filecheck %s

%i1 = "test.op"() : () -> !riscv.reg<a1>
%1 = riscv.li 1 : !riscv.reg

%empty_0 = riscv_snitch.scfgw %i1, %1 : (!riscv.reg<a1>, !riscv.reg) -> !riscv.reg

// CHECK: Operation does not verify: scfgw rd must be ZERO, got !riscv.reg

// -----

%i1 = "test.op"() : () -> !riscv.reg<a1>
%1 = riscv.li 1 : !riscv.reg
%wrong_0 = riscv_snitch.scfgw %i1, %1 : (!riscv.reg<a1>, !riscv.reg) -> !riscv.reg<t0>

// CHECK: Operation does not verify: scfgw rd must be ZERO, got !riscv.reg<t0>

// -----

%i1 = "test.op"() : () -> !riscv.reg<a1>
%empty_1 = riscv_snitch.scfgwi %i1, 1 : (!riscv.reg<a1>) -> !riscv.reg

// CHECK: Operation does not verify: scfgwi rd must be ZERO, got !riscv.reg

// -----

%i1 = "test.op"() : () -> !riscv.reg<a1>
%wrong_1 = riscv_snitch.scfgwi %i1, 1 : (!riscv.reg<a1>) -> !riscv.reg<t0>

// CHECK: Operation does not verify: scfgwi rd must be ZERO, got !riscv.reg<t0>

// -----

%i1 = "test.op"() : () -> !riscv.reg<a1>
%ok_imm = riscv.addi %i1, 1 : (!riscv.reg<a1>) -> !riscv.reg<t0>
%big_imm = riscv.addi %i1, 2048 : (!riscv.reg<a1>) -> !riscv.reg<t0>
Expand Down
14 changes: 7 additions & 7 deletions tests/filecheck/dialects/riscv_snitch/ops.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@ riscv_func.func @xfrep() {
%1 = riscv.get_register : !riscv.reg

// RISC-V extensions
%scfgw = riscv_snitch.scfgw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK: %scfgw = riscv_snitch.scfgw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
%scfgwi_zero = riscv_snitch.scfgwi %0, 42 : (!riscv.reg) -> !riscv.reg<zero>
// CHECK-NEXT: %scfgwi_zero = riscv_snitch.scfgwi %0, 42 : (!riscv.reg) -> !riscv.reg<zero>
riscv_snitch.scfgw %0, %1 : (!riscv.reg, !riscv.reg) -> ()
// CHECK: riscv_snitch.scfgw %0, %1 : (!riscv.reg, !riscv.reg) -> ()
riscv_snitch.scfgwi %0, 42 : (!riscv.reg) -> ()
// CHECK-NEXT: riscv_snitch.scfgwi %0, 42 : (!riscv.reg) -> ()

riscv_snitch.frep_outer %0 {
%add_o = riscv.add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
Expand Down Expand Up @@ -89,7 +89,7 @@ riscv_func.func @xdma() {
riscv_func.func @simd() {
%v = riscv.get_float_register : !riscv.freg
// CHECK: %v = riscv.get_float_register : !riscv.freg

%0 = riscv_snitch.vfmul.s %v, %v : (!riscv.freg, !riscv.freg) -> !riscv.freg
// CHECK-NEXT: %0 = riscv_snitch.vfmul.s %v, %v : (!riscv.freg, !riscv.freg) -> !riscv.freg

Expand All @@ -107,8 +107,8 @@ riscv_func.func @simd() {
// CHECK-GENERIC-NEXT: "riscv_func.func"() ({
// CHECK-GENERIC-NEXT: %0 = "riscv.get_register"() : () -> !riscv.reg
// CHECK-GENERIC-NEXT: %1 = "riscv.get_register"() : () -> !riscv.reg
// CHECK-GENERIC-NEXT: %scfgw = "riscv_snitch.scfgw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK-GENERIC-NEXT: %scfgwi_zero = "riscv_snitch.scfgwi"(%0) {"immediate" = 42 : si12} : (!riscv.reg) -> !riscv.reg<zero>
// CHECK-GENERIC-NEXT: "riscv_snitch.scfgw"(%0, %1) : (!riscv.reg, !riscv.reg) -> ()
// CHECK-GENERIC-NEXT: "riscv_snitch.scfgwi"(%0) {"immediate" = 42 : si12} : (!riscv.reg) -> ()
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_outer"(%{{.*}}) ({
// CHECK-GENERIC-NEXT: %{{.*}} = "riscv.add"(%{{.*}}, %{{.*}}) : (!riscv.reg, !riscv.reg) -> !riscv.reg
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_yield"() : () -> ()
Expand Down
18 changes: 9 additions & 9 deletions tests/filecheck/dialects/snitch/snitch_to_riscv_lowering.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -7,32 +7,32 @@ builtin.module {
// SSR setup sequence for dimension 0
"snitch.ssr_set_dimension_bound"(%bound) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 64 : !riscv.reg
// CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %bound, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK-NEXT: riscv_snitch.scfgw %bound, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
"snitch.ssr_set_dimension_stride"(%stride) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 192 : !riscv.reg
// CHECK-NEXT: %{{.*}} riscv_snitch.scfgw %stride, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK-NEXT: riscv_snitch.scfgw %stride, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
"snitch.ssr_set_dimension_source"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 768 : !riscv.reg
// %{{.*}} = riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
"snitch.ssr_set_dimension_destination"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 896 : !riscv.reg
// CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK-NEXT: riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
// SSR setup sequence for dimension 3
"snitch.ssr_set_dimension_bound"(%bound) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 160 : !riscv.reg
// CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %bound, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK-NEXT: riscv_snitch.scfgw %bound, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
"snitch.ssr_set_dimension_stride"(%stride) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 288 : !riscv.reg
// CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %stride, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK-NEXT: riscv_snitch.scfgw %stride, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
"snitch.ssr_set_dimension_source"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 864 : !riscv.reg
// riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
"snitch.ssr_set_dimension_destination"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 992 : !riscv.reg
// CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK-NEXT: riscv_snitch.scfgw %addr, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
"snitch.ssr_set_stream_repetition"(%rep) {"dm" = #builtin.int<0>}: (!riscv.reg) -> ()
// CHECK: %{{.*}} = riscv.li 32 : !riscv.reg
// CHECK-NEXT: %{{.*}} = riscv_snitch.scfgw %rep, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg<zero>
// CHECK-NEXT: riscv_snitch.scfgw %rep, %{{.*}} : (!riscv.reg, !riscv.reg) -> ()
// On/Off switching sequence
"snitch.ssr_enable"() : () -> ()
// CHECK: riscv.csrrsi 1984, 1
Expand Down
20 changes: 10 additions & 10 deletions tests/filecheck/projects/riscv-backend-paper/pres.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -42,12 +42,12 @@ riscv_func.func @pres_2(%X : !riscv.reg<a0>, %Y : !riscv.reg<a1>, %Z : !riscv.re
riscv_func.func @pres_3(%X : !riscv.reg<a0>, %Y : !riscv.reg<a1>, %Z : !riscv.reg<a2>) {
%zero = riscv.get_register : !riscv.reg<zero>
%n = riscv.addi %zero 63 : (!riscv.reg<zero>) -> !riscv.reg<a3>
%zero_1 = riscv_snitch.scfgwi %n, 95 : (!riscv.reg<a3>) -> (!riscv.reg<zero>)
riscv_snitch.scfgwi %n, 95 : (!riscv.reg<a3>) -> ()
%ub = riscv.addi %zero 8 : (!riscv.reg<zero>) -> !riscv.reg<a3>
%zero_2 = riscv_snitch.scfgwi %n, 223 : (!riscv.reg<a3>) -> !riscv.reg<zero>
%zero_3 = riscv_snitch.scfgwi %X, 768 : (!riscv.reg<a0>) -> !riscv.reg<zero>
%zero_4 = riscv_snitch.scfgwi %Y, 769 : (!riscv.reg<a1>) -> !riscv.reg<zero>
%zero_5 = riscv_snitch.scfgwi %Z, 898 : (!riscv.reg<a2>) -> !riscv.reg<zero>
riscv_snitch.scfgwi %n, 223 : (!riscv.reg<a3>) -> ()
riscv_snitch.scfgwi %X, 768 : (!riscv.reg<a0>) -> ()
riscv_snitch.scfgwi %Y, 769 : (!riscv.reg<a1>) -> ()
riscv_snitch.scfgwi %Z, 898 : (!riscv.reg<a2>) -> ()
%zero_6 = riscv.csrrsi 1984, 1 : () -> !riscv.reg<zero>
%i = riscv.addi %zero, 64 : (!riscv.reg<zero>) -> !riscv.reg<a0>
riscv.label ".loop_body"
Expand All @@ -63,12 +63,12 @@ riscv_func.func @pres_3(%X : !riscv.reg<a0>, %Y : !riscv.reg<a1>, %Z : !riscv.re
riscv_func.func @pres_4(%X : !riscv.reg<a0>, %Y : !riscv.reg<a1>, %Z : !riscv.reg<a2>) {
%zero = riscv.get_register : !riscv.reg<zero>
%n = riscv.addi %zero 63 : (!riscv.reg<zero>) -> !riscv.reg<a3>
%zero_1 = riscv_snitch.scfgwi %n, 95 : (!riscv.reg<a3>) -> (!riscv.reg<zero>)
riscv_snitch.scfgwi %n, 95 : (!riscv.reg<a3>) -> ()
%ub = riscv.addi %zero 8 : (!riscv.reg<zero>) -> !riscv.reg<a3>
%zero_2 = riscv_snitch.scfgwi %n, 223 : (!riscv.reg<a3>) -> !riscv.reg<zero>
%zero_3 = riscv_snitch.scfgwi %X, 768 : (!riscv.reg<a0>) -> !riscv.reg<zero>
%zero_4 = riscv_snitch.scfgwi %Y, 769 : (!riscv.reg<a1>) -> !riscv.reg<zero>
%zero_5 = riscv_snitch.scfgwi %Z, 898 : (!riscv.reg<a2>) -> !riscv.reg<zero>
riscv_snitch.scfgwi %n, 223 : (!riscv.reg<a3>) -> ()
riscv_snitch.scfgwi %X, 768 : (!riscv.reg<a0>) -> ()
riscv_snitch.scfgwi %Y, 769 : (!riscv.reg<a1>) -> ()
riscv_snitch.scfgwi %Z, 898 : (!riscv.reg<a2>) -> ()
%zero_6 = riscv.csrrsi 1984, 1 : () -> !riscv.reg<zero>
%i = riscv.addi %zero, 63 : (!riscv.reg<zero>) -> !riscv.reg<a0>
%x = riscv.get_float_register : !riscv.freg<ft0>
Expand Down
52 changes: 26 additions & 26 deletions xdsl/dialects/riscv.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -675,12 +675,12 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, i20)
attributes["immediate"] = parse_immediate_value(parser, i20)
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(" ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
return {"immediate"}


Expand Down Expand Up @@ -728,14 +728,14 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, si20)
attributes["immediate"] = parse_immediate_value(parser, si20)
if parser.parse_optional_punctuation(","):
attributes["rd"] = parser.parse_attribute()
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(" ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
if self.rd is not None:
printer.print(", ")
printer.print_attribute(self.rd)
Expand Down Expand Up @@ -797,12 +797,12 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, si12)
attributes["immediate"] = parse_immediate_value(parser, si12)
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(", ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
return {"immediate"}


Expand Down Expand Up @@ -858,12 +858,12 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, ui5)
attributes["immediate"] = parse_immediate_value(parser, ui5)
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(", ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
return {"immediate"}


Expand Down Expand Up @@ -922,14 +922,14 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, si12)
attributes["immediate"] = parse_immediate_value(parser, si12)
if parser.parse_optional_punctuation(","):
attributes["rd"] = parser.parse_attribute()
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(", ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
if self.rd is not None:
printer.print(", ")
printer.print_attribute(self.rd)
Expand Down Expand Up @@ -1005,12 +1005,12 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["offset"] = _parse_immediate_value(parser, si12)
attributes["offset"] = parse_immediate_value(parser, si12)
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(", ")
_print_immediate_value(printer, self.offset)
print_immediate_value(printer, self.offset)
return {"offset"}


Expand Down Expand Up @@ -1055,12 +1055,12 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, si12)
attributes["immediate"] = parse_immediate_value(parser, si12)
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(", ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
return {"immediate"}


Expand Down Expand Up @@ -1335,7 +1335,7 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
IntegerType(32),
)
parser.parse_punctuation(",")
attributes["immediate"] = _parse_immediate_value(parser, IntegerType(32))
attributes["immediate"] = parse_immediate_value(parser, IntegerType(32))
if parser.parse_optional_punctuation(",") is not None:
if (flag := parser.parse_str_literal("Expected 'w' flag")) != "w":
parser.raise_error(f"Expected 'w' flag, got '{flag}'")
Expand All @@ -1346,7 +1346,7 @@ def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(" ")
printer.print(self.csr.value.data)
printer.print(", ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
if self.writeonly is not None:
printer.print(', "w"')
return {"csr", "immediate", "writeonly"}
Expand Down Expand Up @@ -1403,14 +1403,14 @@ def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
IntegerType(32),
)
parser.parse_punctuation(",")
attributes["immediate"] = _parse_immediate_value(parser, IntegerType(32))
attributes["immediate"] = parse_immediate_value(parser, IntegerType(32))
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(" ")
printer.print(self.csr.value.data)
printer.print(", ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
return {"csr", "immediate"}


Expand Down Expand Up @@ -2488,12 +2488,12 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, i32)
attributes["immediate"] = parse_immediate_value(parser, i32)
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(" ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
return {"immediate"}

@classmethod
Expand Down Expand Up @@ -3017,12 +3017,12 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, i12)
attributes["immediate"] = parse_immediate_value(parser, i12)
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(", ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
return {"immediate"}


Expand Down Expand Up @@ -3071,12 +3071,12 @@ def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
attributes["immediate"] = _parse_immediate_value(parser, i12)
attributes["immediate"] = parse_immediate_value(parser, i12)
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(", ")
_print_immediate_value(printer, self.immediate)
print_immediate_value(printer, self.immediate)
return {"immediate"}


Expand Down Expand Up @@ -3811,7 +3811,7 @@ def _parse_optional_immediate_value(
return LabelAttr(immediate)


def _parse_immediate_value(
def parse_immediate_value(
parser: Parser, integer_type: IntegerType | IndexType
) -> IntegerAttr[IntegerType | IndexType] | LabelAttr:
return parser.expect(
Expand All @@ -3820,7 +3820,7 @@ def _parse_immediate_value(
)


def _print_immediate_value(printer: Printer, immediate: AnyIntegerAttr | LabelAttr):
def print_immediate_value(printer: Printer, immediate: AnyIntegerAttr | LabelAttr):
match immediate:
case IntegerAttr():
printer.print(immediate.value.data)
Expand Down
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