Decrease address width to 14, and mem size to 64k

wpmed92 · Jan 2, 2023 · db0bc09 · db0bc09
1 parent d9e5099
commit db0bc09
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/chip/rtl/mem.v b/chip/rtl/mem.v
@@ -6,7 +6,7 @@ module mem
     //--------------------------------------------------------------------------
     parameter   NUM_COL             =   4,
     parameter   COL_WIDTH           =   8,
-    parameter   ADDR_WIDTH          =  15,
+    parameter   ADDR_WIDTH          =  14,
     // Addr  Width in bits : 2 *ADDR_WIDTH = RAM Depth
     parameter   DATA_WIDTH      =  NUM_COL*COL_WIDTH  // Data  Width in bits
     //----------------------------------------------------------------------

diff --git a/chip/rtl/mmio.v b/chip/rtl/mmio.v
@@ -23,7 +23,7 @@ module mmio(
     output uart_rxd_out,
     input [3:0] sw
 );
-    wire en_bram = (address >= 0) && (address < 'h8000);
+    wire en_bram = (address >= 0) && (address < 'h32000);
     wire en_gpio = (address >= 'h32000);
     wire [31:0] _bram_out;
     wire [31:0] _gpio_out;
@@ -72,14 +72,14 @@ module mmio(
         .clkA(clk),
         .enaA(1'd1),
         .weA(4'd0),
-        .addrA(pc[16:2]),
+        .addrA(pc[15:2]),
         .dinA(32'd0),
         .doutA(instr_out),
         //Port B is for memory
         .clkB(clk),
         .enaB(en_bram),
         .weB(weB_calc),
-        .addrB(address[16:2]),
+        .addrB(address[15:2]),
         .dinB(data_in_calc),
         .doutB(_bram_out)
     );