[doc] Refactored main "Getting Started" page to make instructions eas…

…ier to follow for new users.

Signed-off-by: Timothy Trippel <[email protected]>

_index.md

@@ -7,12 +7,12 @@ OpenTitan will make the silicon RoT design and implementation more transparent,
 OpenTitan is administered by lowRISC CIC as a collaborative [project]({{< relref "doc/project" >}}) to produce high quality, open IP for instantiation as a full-featured product.
 This repository exists to enable collaboration across partners participating in the OpenTitan project.
 
-To get started using or contributing to the OpenTitan codebase, see the
-[list of user guides]({{< relref "doc/ug" >}}).
-For details on coding styles or how to use our project-specific tooling, see the
-[reference manuals]({{< relref "doc/rm" >}}).
-[This page]({{< relref "hw" >}})
-contains technical documentation on the SoC, the Ibex processor core, and the individual IP blocks.
+## Getting Started
+
+To get started with OpenTitan, see the [Getting Started]({{< relref "doc/ug/getting_started" >}}) page.
+For additional resources when working with OpenTitan, see the [list of user guides]({{< relref "doc/ug" >}}).
+For details on coding styles or how to use our project-specific tooling, see the [reference manuals]({{< relref "doc/rm" >}}).
+Lastly, the [Hardware Dashboard page]({{< relref "hw" >}}) contains technical documentation on the SoC, the Ibex processor core, and the individual IP blocks.
 For questions about how the project is organized, see the [project]({{< relref "doc/project" >}}) landing spot for more information.
 
 ## Repository Structure

doc/ug/design.md

@@ -196,10 +196,10 @@ are checked in.
 There is an over-arching build file in the repository under `hw/Makefile` that builds all of the `regtool` content.
 This is used by an Azure Pipelines pre-submit check script to ensure that the source files produce a generated file that is identical to the one being submitted.
 
-## Getting Started with a Design
+## Getting Started Designing Hardware
 
 The process for getting started with a design involves many steps, including getting clarity on its purpose, its feature set, authorship, documentation, etc.
-These are discussed in the [Getting Started with a Design]({{< relref "getting_started_design.md" >}}) document.
+These are discussed in the [Getting Started Designing Hardware]({{< relref "getting_started_hw_design.md" >}}) document.
 
 ## FPGA vs Silicon
 

doc/ug/dv_methodology/index.md

@@ -177,7 +177,7 @@ Please see the [Ibex DV documentation](https://github.com/lowRISC/opentitan/blob
 The chip level DV effort is aimed at ensuring that all of the IPs are integrated correctly into the chip.
 For IPs that are pre-verified sub-modules, we perform [integration testing](#integration-testing).
 These are simple functional tests written in C which are cross-compiled and run natively on the Ibex core.
-The software compilation flow to enable this is explained in further detail in the [getting started with SW]({{< relref "getting_started_sw.md" >}}) document.
+The software compilation flow to enable this is explained in further detail in the [Getting Started Building SW]({{< relref "getting_started_build_sw.md" >}}) document.
 Further, there is a mechanism for the C test running on the CPU to signal the SystemVerilog testbench the test pass or fail indication based on the observed DUT behavior.
 We also provide an environment knob to 'stub' the CPU and use a TL agent to drive the traffic via the CPU's data channel instead, in cases where more intensive testing is needed.
 <!-- TODO: add link to chip DV document -->