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[rv_core_ibex] Minor clean-up
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- re-name reg to cfg, this removes the reg_reg duplication
- cfg is appropriate here since there is almost no function
  attached to that interface
- minor clean-up of various hjson / python to remove things no
  longer used.

Signed-off-by: Timothy Chen <[email protected]>

[top] Auto gen

Signed-off-by: Timothy Chen <[email protected]>

[sw] Update software base addr

Signed-off-by: Timothy Chen <[email protected]>
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Timothy Chen committed Jul 21, 2021
1 parent a97a64c commit 2b0155a
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Showing 26 changed files with 142 additions and 212 deletions.
4 changes: 2 additions & 2 deletions hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
bus_interfaces: [
{ protocol: "tlul", direction: "host", name: "corei" }
{ protocol: "tlul", direction: "host", name: "cored" }
{ protocol: "tlul", direction: "device", name: "reg" }
{ protocol: "tlul", direction: "device", name: "cfg" }
],
scan: "true", // Enable `scanmode_i` port
scan_reset: "true", // Enable `scan_rst_ni` port
Expand Down Expand Up @@ -284,7 +284,7 @@

regwidth: "32",
registers: {
reg: [
cfg: [
{ multireg: {
cname: "SW_ALERTS_REGWEN",
name: "SW_ALERT_REGWEN",
Expand Down
14 changes: 7 additions & 7 deletions hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -80,8 +80,8 @@ module rv_core_ibex
input lc_ctrl_pkg::lc_tx_t scanmode_i,

// peripheral interface access
input tlul_pkg::tl_h2d_t reg_tl_d_i,
output tlul_pkg::tl_d2h_t reg_tl_d_o,
input tlul_pkg::tl_h2d_t cfg_tl_d_i,
output tlul_pkg::tl_d2h_t cfg_tl_d_o,

// interrupts and alerts
input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
Expand All @@ -93,8 +93,8 @@ module rv_core_ibex
import tlul_pkg::*;

// Register module
rv_core_ibex_reg_reg2hw_t reg2hw;
rv_core_ibex_reg_hw2reg_t hw2reg;
rv_core_ibex_cfg_reg2hw_t reg2hw;
rv_core_ibex_cfg_hw2reg_t hw2reg;

// if pipeline=1, do not allow pass through and always break the path
// if pipeline is 0, passthrough the fifo completely
Expand Down Expand Up @@ -463,11 +463,11 @@ module rv_core_ibex
//////////////////////////////////

logic intg_err;
rv_core_ibex_reg_reg_top u_reg_reg (
rv_core_ibex_cfg_reg_top u_reg_cfg (
.clk_i,
.rst_ni,
.tl_i(reg_tl_d_i),
.tl_o(reg_tl_d_o),
.tl_i(cfg_tl_d_i),
.tl_o(cfg_tl_d_o),
.reg2hw,
.hw2reg,
.intg_err_o (intg_err),
Expand Down
50 changes: 25 additions & 25 deletions ...core_ibex/rtl/rv_core_ibex_reg_reg_top.sv → ...core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -6,15 +6,15 @@

`include "prim_assert.sv"

module rv_core_ibex_reg_reg_top (
module rv_core_ibex_cfg_reg_top (
input clk_i,
input rst_ni,

input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// To HW
output rv_core_ibex_reg_pkg::rv_core_ibex_reg_reg2hw_t reg2hw, // Write
input rv_core_ibex_reg_pkg::rv_core_ibex_reg_hw2reg_t hw2reg, // Read
output rv_core_ibex_reg_pkg::rv_core_ibex_cfg_reg2hw_t reg2hw, // Write
input rv_core_ibex_reg_pkg::rv_core_ibex_cfg_hw2reg_t hw2reg, // Read

// Integrity check errors
output logic intg_err_o,
Expand Down Expand Up @@ -942,28 +942,28 @@ module rv_core_ibex_reg_reg_top (
// Check sub-word write is permitted
always_comb begin
wr_err = (reg_we &
((addr_hit[ 0] & (|(RV_CORE_IBEX_REG_PERMIT[ 0] & ~reg_be))) |
(addr_hit[ 1] & (|(RV_CORE_IBEX_REG_PERMIT[ 1] & ~reg_be))) |
(addr_hit[ 2] & (|(RV_CORE_IBEX_REG_PERMIT[ 2] & ~reg_be))) |
(addr_hit[ 3] & (|(RV_CORE_IBEX_REG_PERMIT[ 3] & ~reg_be))) |
(addr_hit[ 4] & (|(RV_CORE_IBEX_REG_PERMIT[ 4] & ~reg_be))) |
(addr_hit[ 5] & (|(RV_CORE_IBEX_REG_PERMIT[ 5] & ~reg_be))) |
(addr_hit[ 6] & (|(RV_CORE_IBEX_REG_PERMIT[ 6] & ~reg_be))) |
(addr_hit[ 7] & (|(RV_CORE_IBEX_REG_PERMIT[ 7] & ~reg_be))) |
(addr_hit[ 8] & (|(RV_CORE_IBEX_REG_PERMIT[ 8] & ~reg_be))) |
(addr_hit[ 9] & (|(RV_CORE_IBEX_REG_PERMIT[ 9] & ~reg_be))) |
(addr_hit[10] & (|(RV_CORE_IBEX_REG_PERMIT[10] & ~reg_be))) |
(addr_hit[11] & (|(RV_CORE_IBEX_REG_PERMIT[11] & ~reg_be))) |
(addr_hit[12] & (|(RV_CORE_IBEX_REG_PERMIT[12] & ~reg_be))) |
(addr_hit[13] & (|(RV_CORE_IBEX_REG_PERMIT[13] & ~reg_be))) |
(addr_hit[14] & (|(RV_CORE_IBEX_REG_PERMIT[14] & ~reg_be))) |
(addr_hit[15] & (|(RV_CORE_IBEX_REG_PERMIT[15] & ~reg_be))) |
(addr_hit[16] & (|(RV_CORE_IBEX_REG_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(RV_CORE_IBEX_REG_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(RV_CORE_IBEX_REG_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(RV_CORE_IBEX_REG_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(RV_CORE_IBEX_REG_PERMIT[20] & ~reg_be))) |
(addr_hit[21] & (|(RV_CORE_IBEX_REG_PERMIT[21] & ~reg_be)))));
((addr_hit[ 0] & (|(RV_CORE_IBEX_CFG_PERMIT[ 0] & ~reg_be))) |
(addr_hit[ 1] & (|(RV_CORE_IBEX_CFG_PERMIT[ 1] & ~reg_be))) |
(addr_hit[ 2] & (|(RV_CORE_IBEX_CFG_PERMIT[ 2] & ~reg_be))) |
(addr_hit[ 3] & (|(RV_CORE_IBEX_CFG_PERMIT[ 3] & ~reg_be))) |
(addr_hit[ 4] & (|(RV_CORE_IBEX_CFG_PERMIT[ 4] & ~reg_be))) |
(addr_hit[ 5] & (|(RV_CORE_IBEX_CFG_PERMIT[ 5] & ~reg_be))) |
(addr_hit[ 6] & (|(RV_CORE_IBEX_CFG_PERMIT[ 6] & ~reg_be))) |
(addr_hit[ 7] & (|(RV_CORE_IBEX_CFG_PERMIT[ 7] & ~reg_be))) |
(addr_hit[ 8] & (|(RV_CORE_IBEX_CFG_PERMIT[ 8] & ~reg_be))) |
(addr_hit[ 9] & (|(RV_CORE_IBEX_CFG_PERMIT[ 9] & ~reg_be))) |
(addr_hit[10] & (|(RV_CORE_IBEX_CFG_PERMIT[10] & ~reg_be))) |
(addr_hit[11] & (|(RV_CORE_IBEX_CFG_PERMIT[11] & ~reg_be))) |
(addr_hit[12] & (|(RV_CORE_IBEX_CFG_PERMIT[12] & ~reg_be))) |
(addr_hit[13] & (|(RV_CORE_IBEX_CFG_PERMIT[13] & ~reg_be))) |
(addr_hit[14] & (|(RV_CORE_IBEX_CFG_PERMIT[14] & ~reg_be))) |
(addr_hit[15] & (|(RV_CORE_IBEX_CFG_PERMIT[15] & ~reg_be))) |
(addr_hit[16] & (|(RV_CORE_IBEX_CFG_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(RV_CORE_IBEX_CFG_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(RV_CORE_IBEX_CFG_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(RV_CORE_IBEX_CFG_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(RV_CORE_IBEX_CFG_PERMIT[20] & ~reg_be))) |
(addr_hit[21] & (|(RV_CORE_IBEX_CFG_PERMIT[21] & ~reg_be)))));
end
assign alert_test_we = addr_hit[0] & reg_we & !reg_error;

Expand Down
72 changes: 36 additions & 36 deletions hw/ip/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@ package rv_core_ibex_reg_pkg;
parameter int NumAlerts = 4;

// Address widths within the block
parameter int RegAw = 7;
parameter int CfgAw = 7;

//////////////////////////////////////////////
// Typedefs for registers for reg interface //
// Typedefs for registers for cfg interface //
//////////////////////////////////////////////

typedef struct packed {
Expand Down Expand Up @@ -84,7 +84,7 @@ package rv_core_ibex_reg_pkg;
} recov_core_err;
} rv_core_ibex_hw2reg_err_status_reg_t;

// Register -> HW type for reg interface
// Register -> HW type for cfg interface
typedef struct packed {
rv_core_ibex_reg2hw_alert_test_reg_t alert_test; // [271:264]
rv_core_ibex_reg2hw_sw_alert_mreg_t [1:0] sw_alert; // [263:260]
Expand All @@ -94,45 +94,45 @@ package rv_core_ibex_reg_pkg;
rv_core_ibex_reg2hw_dbus_addr_en_mreg_t [1:0] dbus_addr_en; // [129:128]
rv_core_ibex_reg2hw_dbus_addr_matching_mreg_t [1:0] dbus_addr_matching; // [127:64]
rv_core_ibex_reg2hw_dbus_remap_addr_mreg_t [1:0] dbus_remap_addr; // [63:0]
} rv_core_ibex_reg_reg2hw_t;
} rv_core_ibex_cfg_reg2hw_t;

// HW -> register type for reg interface
// HW -> register type for cfg interface
typedef struct packed {
rv_core_ibex_hw2reg_err_status_reg_t err_status; // [7:0]
} rv_core_ibex_reg_hw2reg_t;

// Register offsets for reg interface
parameter logic [RegAw-1:0] RV_CORE_IBEX_ALERT_TEST_OFFSET = 7'h 0;
parameter logic [RegAw-1:0] RV_CORE_IBEX_SW_ALERT_REGWEN_0_OFFSET = 7'h 4;
parameter logic [RegAw-1:0] RV_CORE_IBEX_SW_ALERT_REGWEN_1_OFFSET = 7'h 8;
parameter logic [RegAw-1:0] RV_CORE_IBEX_SW_ALERT_0_OFFSET = 7'h c;
parameter logic [RegAw-1:0] RV_CORE_IBEX_SW_ALERT_1_OFFSET = 7'h 10;
parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET = 7'h 14;
parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET = 7'h 18;
parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET = 7'h 1c;
parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET = 7'h 20;
parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET = 7'h 24;
parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET = 7'h 28;
parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET = 7'h 2c;
parameter logic [RegAw-1:0] RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET = 7'h 30;
parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET = 7'h 34;
parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET = 7'h 38;
parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET = 7'h 3c;
parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET = 7'h 40;
parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET = 7'h 44;
parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET = 7'h 48;
parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET = 7'h 4c;
parameter logic [RegAw-1:0] RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET = 7'h 50;
parameter logic [RegAw-1:0] RV_CORE_IBEX_ERR_STATUS_OFFSET = 7'h 54;

// Reset values for hwext registers and their fields for reg interface
} rv_core_ibex_cfg_hw2reg_t;

// Register offsets for cfg interface
parameter logic [CfgAw-1:0] RV_CORE_IBEX_ALERT_TEST_OFFSET = 7'h 0;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_SW_ALERT_REGWEN_0_OFFSET = 7'h 4;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_SW_ALERT_REGWEN_1_OFFSET = 7'h 8;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_SW_ALERT_0_OFFSET = 7'h c;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_SW_ALERT_1_OFFSET = 7'h 10;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET = 7'h 14;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET = 7'h 18;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET = 7'h 1c;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET = 7'h 20;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET = 7'h 24;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET = 7'h 28;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET = 7'h 2c;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET = 7'h 30;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET = 7'h 34;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET = 7'h 38;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET = 7'h 3c;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET = 7'h 40;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET = 7'h 44;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET = 7'h 48;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET = 7'h 4c;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET = 7'h 50;
parameter logic [CfgAw-1:0] RV_CORE_IBEX_ERR_STATUS_OFFSET = 7'h 54;

// Reset values for hwext registers and their fields for cfg interface
parameter logic [3:0] RV_CORE_IBEX_ALERT_TEST_RESVAL = 4'h 0;
parameter logic [0:0] RV_CORE_IBEX_ALERT_TEST_FATAL_SW_ERR_RESVAL = 1'h 0;
parameter logic [0:0] RV_CORE_IBEX_ALERT_TEST_RECOV_SW_ERR_RESVAL = 1'h 0;
parameter logic [0:0] RV_CORE_IBEX_ALERT_TEST_FATAL_HW_ERR_RESVAL = 1'h 0;
parameter logic [0:0] RV_CORE_IBEX_ALERT_TEST_RECOV_HW_ERR_RESVAL = 1'h 0;

// Register index for reg interface
// Register index for cfg interface
typedef enum int {
RV_CORE_IBEX_ALERT_TEST,
RV_CORE_IBEX_SW_ALERT_REGWEN_0,
Expand All @@ -156,10 +156,10 @@ package rv_core_ibex_reg_pkg;
RV_CORE_IBEX_DBUS_REMAP_ADDR_0,
RV_CORE_IBEX_DBUS_REMAP_ADDR_1,
RV_CORE_IBEX_ERR_STATUS
} rv_core_ibex_reg_id_e;
} rv_core_ibex_cfg_id_e;

// Register width information to check illegal writes for reg interface
parameter logic [3:0] RV_CORE_IBEX_REG_PERMIT [22] = '{
// Register width information to check illegal writes for cfg interface
parameter logic [3:0] RV_CORE_IBEX_CFG_PERMIT [22] = '{
4'b 0001, // index[ 0] RV_CORE_IBEX_ALERT_TEST
4'b 0001, // index[ 1] RV_CORE_IBEX_SW_ALERT_REGWEN_0
4'b 0001, // index[ 2] RV_CORE_IBEX_SW_ALERT_REGWEN_1
Expand Down
2 changes: 1 addition & 1 deletion hw/ip/rv_core_ibex/rv_core_ibex.core
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ filesets:
files:
- rtl/rv_core_ibex_pkg.sv
- rtl/rv_core_ibex_reg_pkg.sv
- rtl/rv_core_ibex_reg_reg_top.sv
- rtl/rv_core_ibex_cfg_reg_top.sv
- rtl/rv_core_ibex.sv
- rtl/rv_core_addr_trans.sv
file_type: systemVerilogSource
Expand Down
41 changes: 0 additions & 41 deletions hw/ip/rv_core_ibex_peri/rv_core_ibex_peri.core
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19 changes: 0 additions & 19 deletions hw/ip/rv_core_ibex_peri/rv_core_ibex_peri_pkg.core
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