[otbn] Make WSR numbers match the implementation

In 19afa99 we swapped the ACC and URND WSRs, but ultimately the documentation wasn't updated to reflect that. (I'm sure I had those changes at some point, seems like they got lost during a rebase.) Signed-off-by: Philipp Wagner <[email protected]>
wk1101 · Jul 20, 2021 · 0f1a9f2 · 0f1a9f2
1 parent cc906c0
commit 0f1a9f2
Showing 1 changed file with 8 additions and 8 deletions.
diff --git a/hw/ip/otbn/doc/_index.md b/hw/ip/otbn/doc/_index.md
@@ -355,14 +355,6 @@ Reads when the cache is empty will cause OTBN to be stalled until a new random n
     </tr>
     <tr>
       <td>0x2</td>
-      <td>RW</td>
-      <td>ACC</td>
-      <td>
-        The accumulator register used by the {{< otbnInsnRef "BN.MULQACC" >}} instruction.
-      </td>
-    </tr>
-    <tr>
-      <td>0x3</td>
       <td>URND</td>
       <td>R</td>
       <td>
@@ -374,6 +366,14 @@ The number is sourced from an LFSR.
 Reads never stall.
       </td>
     </tr>
+    <tr>
+      <td>0x3</td>
+      <td>RW</td>
+      <td>ACC</td>
+      <td>
+        The accumulator register used by the {{< otbnInsnRef "BN.MULQACC" >}} instruction.
+      </td>
+    </tr>
   </tbody>
 </table>