CDP1802 Processor
The processor is a 1:1 analog of the original 1802, and I see no reason to rewrite the original documentation. And what follows is any changes that were made.
- A Full-width 16-bit address bus. If your project requires the 8-bit address bus and uses a latch to create the upper 8-bits, use io_Addr port.
- Debugging strings for checking states in the simulator.
- XTAL output. Clock signals in an FPGA need special handling, you can easily generate this signal.