[aes, pre_dv] Add very basic scratch Verilator testbench for cipher core

This is mainly useful to perform some basic verification of, e.g., a
synthesized version of the AES cipher core and/or to get an
understanding of how to interface the core, e.g., for verifying security
properties.

This is related to lowRISC#19091.

Signed-off-by: Pirmin Vogel <[email protected]>

hw/ip/aes/pre_dv/aes_cipher_core_tb/README.md

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+AES Cipher Core Verilator Testbench
+===================================
+
+This directory contains a very basic, scratch Verilator testbench of the AES
+cipher core. The main use of this testbench is to help understanding how
+to operate and properly interface the AES cipher core, e.g., for evaluating
+security properties.
+
+How to build and run the testbench
+----------------------------------
+
+From the OpenTitan top level execute
+
+   ```sh
+   fusesoc --cores-root=. run --setup \
+     --build lowrisc:dv_verilator:aes_cipher_core_tb
+   ```
+to build the testbench and afterwards
+
+   ```sh
+   ./build/lowrisc_dv_verilator_aes_cipher_core_tb_0/default-verilator/Vaes_cipher_core_tb \
+     --trace
+   ```
+to run it.
+
+Details of the testbench
+------------------------
+
+- `rtl/aes_cipher_core_tb.sv`: SystemVerilog testbench, instantiates and drives
+  the AES cipher core, compares outputs, signals test end and result
+  (pass/fail) to C++ via output ports.
+- `cpp/aes_cipher_core_tb.cc`: Contains main function and instantiation of
+  SimCtrl, reads output ports of DUT and signals simulation termination to
+  Verilator.

hw/ip/aes/pre_dv/aes_cipher_core_tb/aes_cipher_core_tb.core

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+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv_verilator:aes_cipher_core_tb"
+description: "AES Cipher Core Verilator TB"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:ip:aes
+    files:
+      - rtl/aes_cipher_core_tb.sv
+    file_type: systemVerilogSource
+
+  files_dv_verilator:
+    depend:
+      - lowrisc:dv_verilator:simutil_verilator
+
+    files:
+      - cpp/aes_cipher_core_tb.cc
+    file_type: cppSource
+
+targets:
+  default:
+    default_tool: verilator
+    filesets:
+      - files_rtl
+      - files_dv_verilator
+    toplevel: aes_cipher_core_tb
+    tools:
+      verilator:
+        mode: cc
+        verilator_options:
+# Disabling tracing reduces compile times by multiple times, but doesn't have a
+# huge influence on runtime performance. (Based on early observations.)
+          - '--trace'
+          - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
+          - '--trace-structs'
+          - '--trace-params'
+          - '--trace-max-array 1024'
+# compiler flags
+#
+# -O
+#   Optimization levels have a large impact on the runtime performance of the
+#   simulation model. -O2 and -O3 are pretty similar, -Os is slower than -O2/-O3
+          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=aes_cipher_core_tb -g -O0"'
+          - '-LDFLAGS "-pthread -lutil -lelf"'
+          - "-Wall"
+          # XXX: Cleanup all warnings and remove this option
+          # (or make it more fine-grained at least)
+          - "-Wno-fatal"

hw/ip/aes/pre_dv/aes_cipher_core_tb/cpp/aes_cipher_core_tb.cc

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+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <functional>
+#include <iostream>
+#include <signal.h>
+
+#include "Vaes_cipher_core_tb.h"
+#include "sim_ctrl_extension.h"
+#include "verilated_toplevel.h"
+#include "verilator_sim_ctrl.h"
+
+class AESCipherCoreTB : public SimCtrlExtension {
+  using SimCtrlExtension::SimCtrlExtension;
+
+ public:
+  AESCipherCoreTB(aes_cipher_core_tb *top);
+
+  void OnClock(unsigned long sim_time);
+
+ private:
+  aes_cipher_core_tb *top_;
+};
+
+// Constructor:
+// - Set up top_ ptr
+AESCipherCoreTB::AESCipherCoreTB(aes_cipher_core_tb *top)
+    : SimCtrlExtension{}, top_(top) {}
+
+// Function called once every clock cycle from SimCtrl
+void AESCipherCoreTB::OnClock(unsigned long sim_time) {
+  if (top_->test_done_o) {
+    VerilatorSimCtrl::GetInstance().RequestStop(top_->test_passed_o);
+  }
+}
+
+int main(int argc, char **argv) {
+  int ret_code;
+
+  // Init verilog instance
+  aes_cipher_core_tb top;
+
+  // Init sim
+  VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
+  simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
+                 VerilatorSimCtrlFlags::ResetPolarityNegative);
+
+  // Create and register VerilatorSimCtrl extension
+  AESCipherCoreTB aes_cipher_core_tb(&top);
+  simctrl.RegisterExtension(&aes_cipher_core_tb);
+
+  std::cout << "Simulation of AES Cipher Core" << std::endl
+            << "=============================" << std::endl
+            << std::endl;
+
+  // Get pass / fail from Verilator
+  ret_code = simctrl.Exec(argc, argv).first;
+
+  return ret_code;
+}