[aes, pre-dv] Remove test vector redundancies

Firstly, this commit removes some redundant instructions in the test vector sequences, e.g., unnecessary writes to the `CTRL_GCM` register. Secondly, some redundant polls for the `IDLE` bit in the `STATUS` register are replaced with polls for the `INPUT_READY` bit. Signed-off-by: Andrea Caforio <[email protected]>
vogelpi · Dec 13, 2024 · ea6f45c · ea6f45c
1 parent 9824c23
commit ea6f45c
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Showing 5 changed files with 145 additions and 319 deletions.
diff --git a/hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d0.svh b/hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d0.svh
@@ -8,7 +8,7 @@
 // Preamble:
 `define AD_LENGTH 0
 `define DATA_LENGTH 0
-`define NUM_REQUESTS 42
+`define NUM_REQUESTS 41
 
 `define REQUESTS bus_request_t requests[`NUM_REQUESTS] = '{                                         \
   c_dpi_load('{                                                                                     \
@@ -54,7 +54,6 @@
       32'(16)       << AES_CTRL_GCM_NUM_VALID_BYTES_OFFSET |                                        \
       32'(GCM_INIT) << AES_CTRL_GCM_PHASE_OFFSET                                                    \
   ),                                                                                                \
-  read_request(AES_STATUS_OFFSET, 32'(1'b1) << AES_STATUS_IDLE_OFFSET),                             \
                                                                                                     \
   /* Write key registers */                                                                         \
   write_request(AES_KEY_SHARE0_0_OFFSET, 32'h00000000),                                             \

diff --git a/hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d16.svh b/hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d16.svh
@@ -8,7 +8,7 @@
 // Preamble:
 `define AD_LENGTH 0
 `define DATA_LENGTH 16
-`define NUM_REQUESTS 55
+`define NUM_REQUESTS 54
 
 `define REQUESTS bus_request_t requests[`NUM_REQUESTS] = '{                                         \
   c_dpi_load('{                                                                                     \
@@ -54,7 +54,6 @@
       32'(16)       << AES_CTRL_GCM_NUM_VALID_BYTES_OFFSET |                                        \
       32'(GCM_INIT) << AES_CTRL_GCM_PHASE_OFFSET                                                    \
   ),                                                                                                \
-  read_request(AES_STATUS_OFFSET, 32'(1'b1) << AES_STATUS_IDLE_OFFSET),                             \
                                                                                                     \
   /* Write key registers.*/                                                                         \
   write_request(AES_KEY_SHARE0_0_OFFSET, 32'h00000000),                                             \
@@ -93,7 +92,7 @@
       32'(16)       << AES_CTRL_GCM_NUM_VALID_BYTES_OFFSET |                                        \
       32'(GCM_TEXT) << AES_CTRL_GCM_PHASE_OFFSET                                                    \
   ),                                                                                                \
-  read_request(AES_STATUS_OFFSET, 32'(1'b1) << AES_STATUS_IDLE_OFFSET),                             \
+  read_request(AES_STATUS_OFFSET, 32'(1'b1) << AES_STATUS_INPUT_READY_OFFSET),                      \
                                                                                                     \
   write_request(AES_DATA_IN_0_OFFSET, 32'h00000000),                                                \
   write_request(AES_DATA_IN_1_OFFSET, 32'h00000000),                                                \