[top_earlgrey] Reduce number of PRINCE half rounds for main SRAM

This commit reduces the number of PRINCE half rounds for the scrambling
of the main SRAM to 2 half rounds as used in the past. This is done
to reduce timing pressure.

Signed-off-by: Pirmin Vogel <[email protected]>

hw/ip/prim/doc/prim_ram_1p_scr.md

@@ -2,9 +2,10 @@
 
 # Overview
 
-The scrambling primitive `prim_ram_1p_scr` employs a reduced-round (7 instead of 11) PRINCE block cipher in CTR mode to scramble the data.
+The scrambling primitive `prim_ram_1p_scr` employs a reduced-round (5 or 7 instead of 11) PRINCE block cipher in CTR mode to scramble the data.
 The PRINCE lightweight block cipher has been selected due to its low latency and low area characteristics, see also [prim_prince](./prim_prince.md) for more information on PRINCE.
-The number of rounds is reduced to 7 in order to ease timing pressure and ensure single cycle operation (the number of rounds can always be increased if it turns out that there is enough timing slack).
+In the default configuration, the number of rounds is reduced to 7 in order to ease timing pressure and ensure single cycle operation (the number of rounds can always be increased via the `NumPrinceRoundsHalf` parameter if it turns out that there is enough timing slack).
+To ease timing closure at the top level, the number of rounds used for scrambling the main SRAM and the instruction cache of the Ibex processor core is 5 (`NumPrinceRoundsHalf` = 2).
 
 In [CTR mode](https://en.wikipedia.org/wiki/Block_cipher_mode_of_operation#Counter_(CTR)), the block cipher is used to encrypt a 64bit IV with the scrambling key in order to create a 64bit keystream block that is bitwise XOR'ed with the data in order to transform plaintext into ciphertext and vice versa.
 The IV is assembled by concatenating a nonce with the word address.

hw/ip/sram_ctrl/dv/sram_ctrl_main_sim_cfg.hjson

@@ -13,5 +13,5 @@
   // These parameters are used for top_earlgrey main sram
   build_opts: ["+define+SRAM_ADDR_WIDTH=15",
                "+define+INSTR_EXEC=1",
-               "+define+NUM_PRINCE_ROUNDS_HALF=3"]
+               "+define+NUM_PRINCE_ROUNDS_HALF=2"]
 }

hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson

@@ -7265,6 +7265,7 @@
       param_decl:
       {
         InstrExec: "1"
+        NumPrinceRoundsHalf: "2"
       }
       base_addrs:
       {
@@ -7353,7 +7354,7 @@
           name: NumPrinceRoundsHalf
           desc: Number of PRINCE half rounds for the SRAM scrambling feature
           type: int
-          default: "3"
+          default: "2"
           expose: "true"
           name_top: SramCtrlMainNumPrinceRoundsHalf
         }

hw/top_earlgrey/data/top_earlgrey.hjson

@@ -727,6 +727,7 @@
       reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"},
       param_decl: {
         InstrExec: "1",
+        NumPrinceRoundsHalf: "2",
       },
       base_addrs: {regs: "0x411C0000", ram: "0x10000000"},
       // Memory regions must be associated with a dedicated

hw/top_earlgrey/dv/tb/tb.sv

@@ -555,6 +555,7 @@ module tb;
           .depth ($size(`RAM_MAIN_MEM_HIER)),
           .n_bits($bits(`RAM_MAIN_MEM_HIER)),
           .err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32),
+          .num_prince_rounds_half(2),
           .system_base_addr    (top_earlgrey_pkg::TOP_EARLGREY_RAM_MAIN_BASE_ADDR));
       `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamMain0], `RAM_MAIN_MEM_HIER)
 

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

@@ -97,7 +97,7 @@ module top_earlgrey #(
   // parameters for edn1
   // parameters for sram_ctrl_main
   parameter bit SramCtrlMainInstrExec = 1,
-  parameter int SramCtrlMainNumPrinceRoundsHalf = 3,
+  parameter int SramCtrlMainNumPrinceRoundsHalf = 2,
   // parameters for rom_ctrl
   parameter RomCtrlBootRomInitFile = "",
   parameter bit SecRomCtrlDisableScrambling = 1'b0,