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[tlul, shim] TLUL Shim Adapter and Testbench #65

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[tlul, shim] TLUL Shim Adapter and Testbench

[tlul, shim] TLUL Shim Adapter and Testbench #65

Triggered via pull request November 12, 2024 16:38
@andrea-caforioandrea-caforio
synchronize #3
andrea-caforio:aes_gcm_tlul_shim_adapter
Status Failure
Total duration 1d 9h 57m 13s
Artifacts 3

ci.yml

on: pull_request
Lint (quick)
2m 57s
Lint (quick)
Lint (slow)
12m 49s
Lint (slow)
Airgapped build
11m 38s
Airgapped build
Verible lint
3m 25s
Verible lint
Verilated English Breakfast
7m 52s
Verilated English Breakfast
CW305's Bitstream
0s
CW305's Bitstream
Build Docker Containers
3m 5s
Build Docker Containers
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8 errors
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Verilog style lint of DV sources with Verible failed. Run 'util/dvsim/dvsim.py -t veriblelint hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson' and fix all errors.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
CW305's Bitstream
This request was automatically failed because there were no enabled runners online to process the request for more than 1 days.

Artifacts

Produced during runtime
Name Size
verilated_englishbreakfast
6.6 MB
vogelpi~opentitan~NJD4HA.dockerbuild
19.7 KB
vogelpi~opentitan~SVF5NF.dockerbuild
97.6 KB