Upgrade to Chisel 3.6 (#57)

* port to Chisel 3.6 * use circt to generate Verilog * use correct firtool version * Tile.sv * update sbt version * ci: modernize
ucb-bar · Sep 21, 2023 · f894586 · f894586
1 parent 3473cfd
commit f894586
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diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -7,47 +7,39 @@ jobs:
     name: Scala Unit Tests
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
     - name: Install Tabby OSS Cad Suite (from YosysHQ)
-      uses: YosysHQ/setup-oss-cad-suite@v1
+      uses: ./.github/workflows/setup-oss-cad-suite
       with:
         osscadsuite-version: '2022-02-02'
-    - name: Setup Scala
-      uses: olafurpg/setup-scala@v11
-      with:
-        java-version: [email protected]
     - name: Scala Unit Tests
       run: sbt "testOnly -- -l IntegrationTest"
 
   integration-tests:
     name: Scala Integration Tests
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
     - name: Install Tabby OSS Cad Suite (from YosysHQ)
-      uses: YosysHQ/setup-oss-cad-suite@v1
+      uses: ./.github/workflows/setup-oss-cad-suite
       with:
         osscadsuite-version: '2022-02-02'
-    - name: Setup Scala
-      uses: olafurpg/setup-scala@v11
-      with:
-        java-version: [email protected]
     - name: Scala Integration Tests
       run: sbt "testOnly -- -n IntegrationTest"
 
   make-integration-tests:
     name: Makefile based Integration Tests
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
     - name: Install Tabby OSS Cad Suite (from YosysHQ)
-      uses: YosysHQ/setup-oss-cad-suite@v1
+      uses: ./.github/workflows/setup-oss-cad-suite
       with:
         osscadsuite-version: '2022-02-02'
-    - name: Setup Scala
-      uses: olafurpg/setup-scala@v11
+    - name: Install CIRCT
+      uses: ./.github/workflows/install-circt
       with:
-        java-version: [email protected]
+        version: 'firtool-1.37.0'
     - name: Makefile Integration Tests
       run: make run-tests
 
@@ -56,9 +48,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout
-        uses: actions/checkout@v2
-      - name: Setup Scala
-        uses: olafurpg/setup-scala@v10
+        uses: actions/checkout@v3
       - name: Documentation
         id: doc
         run: sbt doc

diff --git a/.github/workflows/install-circt/action.yml b/.github/workflows/install-circt/action.yml
@@ -0,0 +1,25 @@
+name: Install CIRCT
+
+inputs:
+  version:
+    description: 'version to install'
+    required: false
+    default: 'firtool-1.43.0'
+
+runs:
+  using: composite
+  steps:
+    - id: cache-circt
+      uses: actions/cache@v3
+      with:
+        path: circt
+        key: circt-${{ runner.os }}-${{ inputs.version }}
+
+    - shell: bash
+      if: steps.cache-circt.outputs.cache-hit != 'true'
+      run: |
+        mkdir circt
+        wget -q -O - https://github.com/llvm/circt/releases/download/${{ inputs.version }}/firrtl-bin-ubuntu-20.04.tar.gz | tar -zx -C circt/ --strip-components 1
+
+    - shell: bash
+      run: echo "$(pwd)/circt/bin" >> $GITHUB_PATH
diff --git a/.github/workflows/setup-oss-cad-suite/action.yml b/.github/workflows/setup-oss-cad-suite/action.yml
@@ -0,0 +1,27 @@
+name: Setup OSS CAD Suite
+
+inputs:
+  osscadsuite-version:
+    description: 'version to install'
+    required: true
+
+runs:
+  using: composite
+  steps:
+    - id: cache-oss-cad-suite
+      uses: actions/cache@v3
+      with:
+        path: oss-cad-suite
+        key: oss-cad-suite-${{ runner.os }}-${{ inputs.osscadsuite-version }}
+
+    - shell: bash
+      if: steps.cache-oss-cad-suite.outputs.cache-hit != 'true'
+      run: |
+        VERSION=${{ inputs.osscadsuite-version }}
+        ARTIFACT=oss-cad-suite-linux-x64-$(echo $VERSION | tr -d '-')
+        wget -q -O - https://github.com/YosysHQ/oss-cad-suite-build/releases/download/${VERSION}/${ARTIFACT}.tgz | tar -zx
+
+    # Add the CAD Suite to the PATH
+    - shell: bash
+      run: echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH
+
diff --git a/Makefile b/Makefile
@@ -12,10 +12,10 @@ SBT_FLAGS = -ivy $(base_dir)/.ivy2
 sbt:
 	$(SBT) $(SBT_FLAGS)
 
-compile: $(gen_dir)/Tile.v
+compile: $(gen_dir)/Tile.sv
 
-$(gen_dir)/Tile.v: $(wildcard $(src_dir)/scala/*.scala)
-	$(SBT) $(SBT_FLAGS) "run $(gen_dir)"
+$(gen_dir)/Tile.sv: $(wildcard $(src_dir)/scala/*.scala)
+	$(SBT) $(SBT_FLAGS) "run --target-dir=$(gen_dir)"
 
 CXXFLAGS += -std=c++11 -Wall -Wno-unused-variable
 
@@ -25,7 +25,7 @@ VERILATOR_FLAGS = --assert -Wno-STMTDLY -O3 --trace --threads $(nproc)\
 	--top-module Tile -Mdir $(gen_dir)/VTile.csrc \
 	-CFLAGS "$(CXXFLAGS) -include $(gen_dir)/VTile.csrc/VTile.h" 
 
-$(base_dir)/VTile: $(gen_dir)/Tile.v $(src_dir)/cc/top.cc $(src_dir)/cc/mm.cc $(src_dir)/cc/mm.h
+$(base_dir)/VTile: $(gen_dir)/Tile.sv $(src_dir)/cc/top.cc $(src_dir)/cc/mm.cc $(src_dir)/cc/mm.h
 	$(VERILATOR) $(VERILATOR_FLAGS) -o $@ $< $(word 2, $^) $(word 3, $^)
 	$(MAKE) -C $(gen_dir)/VTile.csrc -f VTile.mk
 

diff --git a/build.sbt b/build.sbt
@@ -2,14 +2,14 @@ ThisBuild / scalaVersion     := "2.13.7"
 ThisBuild / version          := "2.5.0"
 ThisBuild / organization     := "edu.berkeley.cs"
 
-val chiselVersion = "3.5.1"
+val chiselVersion = "3.6.0"
 
 lazy val root = (project in file("."))
   .settings(
     name := "riscv-mini",
     libraryDependencies ++= Seq(
       "edu.berkeley.cs" %% "chisel3" % chiselVersion,
-      "edu.berkeley.cs" %% "chiseltest" % "0.5.1" % "test"
+      "edu.berkeley.cs" %% "chiseltest" % "0.6.2" % "test"
     ),
     scalacOptions ++= Seq(
       "-language:reflectiveCalls",

diff --git a/project/build.properties b/project/build.properties
@@ -1 +1 @@
-sbt.version=1.5.5
+sbt.version=1.8.2
diff --git a/src/main/scala/mini/Alu.scala b/src/main/scala/mini/Alu.scala
@@ -41,9 +41,7 @@ class AluSimple(val width: Int) extends Alu {
 
   val shamt = io.B(4, 0).asUInt
 
-  io.out := MuxLookup(
-    io.alu_op,
-    io.B,
+  io.out := MuxLookup(io.alu_op, io.B)(
     Seq(
       ALU_ADD -> (io.A + io.B),
       ALU_SUB -> (io.A - io.B),

diff --git a/src/main/scala/mini/CSR.scala b/src/main/scala/mini/CSR.scala
@@ -235,23 +235,19 @@ class CSR(val xlen: Int) extends Module {
   val csrValid = csrFile.map(_._1 === csr_addr).reduce(_ || _)
   val csrRO = csr_addr(11, 10).andR || csr_addr === CSR.mtvec || csr_addr === CSR.mtdeleg
   val wen = io.cmd === CSR.W || io.cmd(1) && rs1_addr.orR
-  val wdata = MuxLookup(
-    io.cmd,
-    0.U,
+  val wdata = MuxLookup(io.cmd, 0.U)(
     Seq(
       CSR.W -> io.in,
       CSR.S -> (io.out | io.in),
       CSR.C -> (io.out & ~io.in)
     )
   )
   val iaddrInvalid = io.pc_check && io.addr(1)
-  val laddrInvalid = MuxLookup(
-    io.ld_type,
-    false.B,
+  val laddrInvalid = MuxLookup(io.ld_type, false.B)(
     Seq(Control.LD_LW -> io.addr(1, 0).orR, Control.LD_LH -> io.addr(0), Control.LD_LHU -> io.addr(0))
   )
   val saddrInvalid =
-    MuxLookup(io.st_type, false.B, Seq(Control.ST_SW -> io.addr(1, 0).orR, Control.ST_SH -> io.addr(0)))
+    MuxLookup(io.st_type, false.B)(Seq(Control.ST_SW -> io.addr(1, 0).orR, Control.ST_SH -> io.addr(0)))
   io.expt := io.illegal || iaddrInvalid || laddrInvalid || saddrInvalid ||
     io.cmd(1, 0).orR && (!csrValid || !privValid) || wen && csrRO ||
     (privInst && !privValid) || isEcall || isEbreak

diff --git a/src/main/scala/mini/Cache.scala b/src/main/scala/mini/Cache.scala
@@ -3,7 +3,6 @@
 package mini
 
 import chisel3._
-import chisel3.experimental.ChiselEnum
 import chisel3.util._
 import junctions._
 
@@ -125,7 +124,7 @@ class Cache(val p: CacheConfig, val nasti: NastiBundleParameters, val xlen: Int)
     dataMem.zipWithIndex.foreach {
       case (mem, i) =>
         val data = VecInit.tabulate(wBytes)(k => wdata(i * xlen + (k + 1) * 8 - 1, i * xlen + k * 8))
-        mem.write(idx_reg, data, wmask((i + 1) * wBytes - 1, i * wBytes).asBools())
+        mem.write(idx_reg, data, wmask((i + 1) * wBytes - 1, i * wBytes).asBools)
         mem.suggestName(s"dataMem_${i}")
     }
   }

diff --git a/src/main/scala/mini/Datapath.scala b/src/main/scala/mini/Datapath.scala
@@ -141,9 +141,7 @@ class Datapath(val conf: CoreConfig) extends Module {
   io.dcache.req.valid := !stall && (io.ctrl.st_type.orR || io.ctrl.ld_type.orR)
   io.dcache.req.bits.addr := daddr
   io.dcache.req.bits.data := rs2 << woffset
-  io.dcache.req.bits.mask := MuxLookup(
-    Mux(stall, st_type, io.ctrl.st_type),
-    "b0000".U,
+  io.dcache.req.bits.mask := MuxLookup(Mux(stall, st_type, io.ctrl.st_type), "b0000".U)(
     Seq(ST_SW -> "b1111".U, ST_SH -> ("b11".U << alu.io.sum(1, 0)), ST_SB -> ("b1".U << alu.io.sum(1, 0)))
   )
 
@@ -172,9 +170,7 @@ class Datapath(val conf: CoreConfig) extends Module {
   // Load
   val loffset = (ew_reg.alu(1) << 4.U).asUInt | (ew_reg.alu(0) << 3.U).asUInt
   val lshift = io.dcache.resp.bits.data >> loffset
-  val load = MuxLookup(
-    ld_type,
-    io.dcache.resp.bits.data.zext,
+  val load = MuxLookup(ld_type, io.dcache.resp.bits.data.zext)(
     Seq(
       LD_LH -> lshift(15, 0).asSInt,
       LD_LB -> lshift(7, 0).asSInt,
@@ -198,9 +194,7 @@ class Datapath(val conf: CoreConfig) extends Module {
 
   // Regfile Write
   val regWrite =
-    MuxLookup(
-      wb_sel,
-      ew_reg.alu.zext,
+    MuxLookup(wb_sel, ew_reg.alu.zext)(
       Seq(WB_MEM -> load, WB_PC4 -> (ew_reg.pc + 4.U).zext, WB_CSR -> csr.io.out.zext)
     ).asUInt
 

diff --git a/src/main/scala/mini/ImmGen.scala b/src/main/scala/mini/ImmGen.scala
@@ -26,9 +26,7 @@ class ImmGenWire(val xlen: Int) extends ImmGen {
   val Jimm = Cat(io.inst(31), io.inst(19, 12), io.inst(20), io.inst(30, 25), io.inst(24, 21), 0.U(1.W)).asSInt
   val Zimm = io.inst(19, 15).zext
 
-  io.out := MuxLookup(
-    io.sel,
-    Iimm & (-2).S,
+  io.out := MuxLookup(io.sel, Iimm & (-2).S)(
     Seq(IMM_I -> Iimm, IMM_S -> Simm, IMM_B -> Bimm, IMM_U -> Uimm, IMM_J -> Jimm, IMM_Z -> Zimm)
   ).asUInt
 }

diff --git a/src/main/scala/mini/Main.scala b/src/main/scala/mini/Main.scala
@@ -2,23 +2,15 @@
 
 package mini
 
-import chisel3.stage.ChiselGeneratorAnnotation
-import firrtl.options.TargetDirAnnotation
-
+import circt.stage.ChiselStage
 object Main extends App {
-  val targetDirectory = args.head
   val config = MiniConfig()
-  new chisel3.stage.ChiselStage().execute(
-    args,
-    Seq(
-      ChiselGeneratorAnnotation(() =>
-        new Tile(
-          coreParams = config.core,
-          nastiParams = config.nasti,
-          cacheParams = config.cache
-        )
-      ),
-      TargetDirAnnotation(targetDirectory)
-    )
+  ChiselStage.emitSystemVerilogFile(
+    new Tile(
+      coreParams = config.core,
+      nastiParams = config.nasti,
+      cacheParams = config.cache
+    ),
+    args
   )
 }
diff --git a/src/main/scala/mini/Tile.scala b/src/main/scala/mini/Tile.scala
@@ -3,7 +3,6 @@
 package mini
 
 import chisel3._
-import chisel3.experimental.ChiselEnum
 import chisel3.util._
 import junctions._
 

diff --git a/src/test/scala/mini/CacheTests.scala b/src/test/scala/mini/CacheTests.scala
@@ -3,7 +3,6 @@
 package mini
 
 import chisel3._
-import chisel3.experimental.ChiselEnum
 import chisel3.util._
 import chisel3.testers._
 import junctions._

diff --git a/src/test/scala/mini/DatapathTests.scala b/src/test/scala/mini/DatapathTests.scala
@@ -3,7 +3,6 @@
 package mini
 
 import chisel3._
-import chisel3.experimental.ChiselEnum
 import chisel3.testers._
 import chisel3.util._
 import chiseltest._

diff --git a/src/test/scala/mini/TileTester.scala b/src/test/scala/mini/TileTester.scala
@@ -3,7 +3,6 @@
 package mini
 
 import chisel3._
-import chisel3.experimental.ChiselEnum
 import chisel3.testers._
 import chisel3.util._
 import chisel3.util.experimental.loadMemoryFromFileInline