merge in mlsys tutorial changes

ucb-bar · Nov 23, 2022 · fd92323 · fd92323
2 parents d2922c6 + 65bd41d
commit fd92323
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Showing 3 changed files with 4 additions and 4 deletions.
diff --git a/.github/scripts/build-toolchains.sh b/.github/scripts/build-toolchains.sh
@@ -30,6 +30,6 @@ if [ ! -d "$INSTALL_DIR" ]; then
     cd $HOME
 
     # init all submodules including the tools (doesn't use CI_MAKE_PROC due to mem. constraints)
-    CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=$CI_MAKE_NPROC $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh esp-tools
+    CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=$CI_MAKE_NPROC $LOCAL_CHIPYARD_DIR/build-setup.sh --skip-conda esp-tools
 fi
 
diff --git a/scripts/build-midas.sh b/scripts/build-midas.sh
@@ -56,7 +56,7 @@ fi
 export SYSLIBS=" $SYSLIBS -l:libdwarf.so -l:libelf.so -lz -lgmp "
 
 cd ../../sims/firesim/
-source sourceme-f1-manager.sh &> build.log
+source sourceme-f1-manager.sh --skip-ssh-setup &> build.log
 
 cd sim/
 make ${simulator}${debug} TARGET_CONFIG=${dram_model}_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.CustomGemminiSoCConfig

diff --git a/src/main/scala/gemmini/CustomSoCConfigs.scala b/src/main/scala/gemmini/CustomSoCConfigs.scala
@@ -10,10 +10,10 @@ class CustomGemminiSoCConfig extends Config(
   new chipyard.config.WithL2TLBs(512) ++
 
   new freechips.rocketchip.subsystem.WithInclusiveCache(
-    nBanks = 1,
     nWays = 8,
     capacityKB = 512,
-    outerLatencyCycles = 40
+    outerLatencyCycles = 40,
+    subBankingFactor = 4
   ) ++
 
   // Set the number of CPUs you want to create