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FPGA bugfix
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MCU bugfix
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@tpunix
tpunix committed Nov 11, 2023
1 parent 19b2e5c commit d12cadb
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Showing 13 changed files with 332 additions and 116 deletions.
36 changes: 28 additions & 8 deletions FPGA/SSMaster.v
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,10 @@

// version 0.1: first step.
// 0.2: for HW1.2
// 0.3:
// 0.4: support put_sector_data
// 0.5: CDC bug fix


module SSMaster(
// System
Expand Down Expand Up @@ -227,9 +231,10 @@ module SSMaster(
if(NRESET==0) begin
st_reg_ctrl <= 0;
st_reg_spi <= 3'b111;
st_reg_sdram <= 12'b11_1100001101; // type:64MB refcnt: 0x30d(7.81us)
end else if(st_wr_start==1) begin
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h04) st_reg_ctrl <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h16) st_reg_spi <= ST_AD[3:1];
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h16) {st_reg_sdram, st_reg_spi} <= ST_AD[15:1];
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h20) ss_resp1 <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h22) ss_resp2 <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h24) ss_resp3 <= ST_AD;
Expand Down Expand Up @@ -369,16 +374,17 @@ module SSMaster(
begin
st_reg_data_out <=
(fsmc_addr[7:0]==8'h00)? 16'h5253 : // ID: "SR"
(fsmc_addr[7:0]==8'h02)? 16'h1204 : // ver: HW1.2 && SW0.4
(fsmc_addr[7:0]==8'h02)? 16'h1205 : // ver: HW1.2 && SW0.5
(fsmc_addr[7:0]==8'h04)? st_reg_ctrl :
(fsmc_addr[7:0]==8'h06)? st_reg_stat :
(fsmc_addr[7:0]==8'h08)? st_fifo_data_out :
(fsmc_addr[7:0]==8'h0a)? st_fifo_data_out :
(fsmc_addr[7:0]==8'h0c)? st_fifo_stat :
(fsmc_addr[7:0]==8'h0e)? st_fifo_rcnt :
(fsmc_addr[7:0]==8'h10)? ss_reg_cmd :
(fsmc_addr[7:0]==8'h12)? ss_reg_data :
(fsmc_addr[7:0]==8'h14)? ss_reg_ctrl :
(fsmc_addr[7:0]==8'h16)? {12'b0, EPCS_CS, EPCS_CLK, EPCS_DI, EPCS_DO} :
(fsmc_addr[7:0]==8'h16)? {st_reg_sdram, EPCS_CS, EPCS_CLK, EPCS_DI, EPCS_DO} :

(fsmc_addr[7:0]==8'h18)? ss_resp1 :
(fsmc_addr[7:0]==8'h1a)? ss_resp2 :
Expand Down Expand Up @@ -440,7 +446,7 @@ module SSMaster(

always @(posedge mclk)
begin
sscs_s0 <= (SS_CS0 & SS_CS1 & SS_CS2);
sscs_s0 <= (SS_CS0 & SS_CS1 & SS_CS2) | ~SS_FC1;
sscs_s1 <= sscs_s0;
sscs_s2 <= sscs_s1;
sscs_s3 <= sscs_s2;
Expand All @@ -463,7 +469,7 @@ module SSMaster(
(SS_RD==0 && ss_cdc_cs==1)? ss_cdc_data_out :
16'hzzzz;

assign SS_DATA_OE = (SS_CS0==1 && SS_CS1==1 && (SS_CS2==1 || (ss_cdc_cs==1 && SS_RD==0 && ss_cdc_en==0)));
assign SS_DATA_OE = ~SS_FC1 | (SS_CS0==1 && SS_CS1==1 && (SS_CS2==1 || (ss_cdc_cs==1 && SS_RD==0 && ss_cdc_en==0)));

assign SS_DATA_DIR = (SS_WR0 & SS_WR1);

Expand Down Expand Up @@ -497,7 +503,7 @@ module SSMaster(
begin
ss_bcr_data_out <=
(SS_ADDR[5:1]==5'b00_000)? 16'h5253 : // ID: "SR"
(SS_ADDR[5:1]==5'b00_001)? 16'h1204 : // ver: HW1.2 && SW0.4
(SS_ADDR[5:1]==5'b00_001)? 16'h1205 : // ver: HW1.2 && SW0.5
(SS_ADDR[5:2]==4'b00_01 )? ss_reg_ctrl :
(SS_ADDR[5:2]==4'b00_10 )? ss_reg_stat :
(SS_ADDR[5:1]==5'b00_110)? ss_reg_timer[31:16] :
Expand Down Expand Up @@ -594,6 +600,19 @@ module SSMaster(
.full(fifo_full)
);

// Saturn set and STM32 reset
reg[15:0] st_fifo_rcnt;
always @(negedge NRESET or posedge mclk)
begin
if(NRESET==0)
st_fifo_rcnt <= 4'b0000;
else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h0e)
st_fifo_rcnt <= 0;
else if(ss_fifo_read)
st_fifo_rcnt <= st_fifo_rcnt+1'b1;
end


///////////////////////////////////////////////////////
// SATURN CDC //
///////////////////////////////////////////////////////
Expand Down Expand Up @@ -649,7 +668,8 @@ module SSMaster(
// SDRAM //
///////////////////////////////////////////////////////


reg[11:0] st_reg_sdram;

// STM32 is LittleEndian system
wire[25:0] st_ram_addr = {2'b0, fsmc_addr[23:0]};
wire[ 1:0] st_mask = {ST_BL1,ST_BL0};
Expand Down Expand Up @@ -689,7 +709,7 @@ module SSMaster(
NRESET, mclk,
ss_ram_cs, ss_rd_start, ss_wr_start, ss_mask, ss_ram_wait, ss_ram_addr, ss_ram_din, ss_ram_dout,
st_ram_cs, st_rd_start, st_wr_start, st_mask, st_ram_wait, st_ram_addr, ST_AD, st_ram_data_out,
SD_CKE, SD_CS, SD_RAS, SD_CAS, SD_WE, SD_ADDR, SD_BA, SD_DQM, SD_DQ, ss_refresh
SD_CKE, SD_CS, SD_RAS, SD_CAS, SD_WE, SD_ADDR, SD_BA, SD_DQM, SD_DQ, ss_refresh, st_reg_sdram
);

assign SD_CLK = sdclk;
Expand Down
5 changes: 3 additions & 2 deletions FPGA/memhub.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ module memhub(
cs_a, rd_a, wr_a, mask_a, nwait_a, addr_a, wdata_a, rdata_a,
cs_b, rd_b, wr_b, mask_b, nwait_b, addr_b, wdata_b, rdata_b,
sd_cke, sd_cs, sd_ras, sd_cas, sd_we, sd_addr, sd_ba, sd_dqm, sd_data,
ext_refresh
ext_refresh, reg_sdram
);

///////////////////////////////////////////////////////
Expand Down Expand Up @@ -50,6 +50,7 @@ module memhub(
output[ 1:0] sd_dqm;
inout [15:0] sd_data;
input ext_refresh;
input [11:0] reg_sdram;


///////////////////////////////////////////////////////
Expand Down Expand Up @@ -186,7 +187,7 @@ module memhub(
wire sd_oe;

tsdram _tsd(
reset, clk,
reset, clk, reg_sdram,
ext_refresh, cmd_req, cmd_ack, cmd_mask, cmd_addr, cmd_din, cmd_dout, data_valid,
sd_cke, sd_cs, sd_ras, sd_cas, sd_we, sd_addr, sd_ba, sd_dqm, sd_data, sd_dout, sd_oe
);
Expand Down
40 changes: 34 additions & 6 deletions FPGA/tsdram.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
module tsdram(
reset,
clk,
reg_sdram,

ext_refresh,
cmd_req,
Expand Down Expand Up @@ -37,6 +38,7 @@ module tsdram(

input reset;
input clk;
input [11:0] reg_sdram;

input ext_refresh;
input [ 1:0] cmd_req;
Expand Down Expand Up @@ -87,15 +89,40 @@ module tsdram(
///////////////////////////////////////////////////////

// A31 - A26 [A25 - A13] [A12 A11] [A10 - A1] A0
// [R12 - R0] [ B1 B0] [ C9 - C0]
// [R12 - R0] [ B1 B0] [ C9 - C0] 64MB
//
// A31 - A25 [A24 - A12] [A11 A10] [ A9 - A1] A0
// [R12 - R0] [ B1 B0] [ C8 - C0] 32MB
//
// A31 - A24 [A23 - A12] [A11 A10] [ A9 - A1] A0
// [R11 - R0] [ B1 B0] [ C8 - C0] 16MB
//
// A31 - A23 [A22 - A11] [A10 A9] [ A8 - A1] A0
// [R11 - R0] [ B1 B0] [ C7 - C0] 8MB

localparam BANK_POS = COL_BITS+1;
localparam ROW_POS = BANK_POS+2;

wire[ROW_BITS-1:0] col_addr = {3'b001, {(10-COL_BITS){1'b0}}, cmd_addr[COL_BITS:1]};

wire[1:0] bank_addr = cmd_addr[COL_BITS+2:COL_BITS+1];
wire[ROW_BITS-1:0] row_addr = cmd_addr[ROW_BITS+COL_BITS+2:COL_BITS+3];
// wire[ROW_BITS-1:0] col_addr = {3'b001, {(10-COL_BITS){1'b0}}, cmd_addr[COL_BITS:1]};
// wire[1:0] bank_addr = cmd_addr[COL_BITS+2:COL_BITS+1];
// wire[ROW_BITS-1:0] row_addr = cmd_addr[ROW_BITS+COL_BITS+2:COL_BITS+3];

wire[1:0] sdtype = reg_sdram[11:10];
wire[12:0] col_addr =
(sdtype==2'b11)? {3'b001, cmd_addr[10:1]} :
(sdtype==2'b10)? {4'b0010, cmd_addr[ 9:1]} :
(sdtype==2'b01)? {4'b0010, cmd_addr[ 9:1]} :
{5'b00100, cmd_addr[ 8:1]} ;
wire[1:0] bank_addr =
(sdtype==2'b11)? cmd_addr[12:11] :
(sdtype==2'b10)? cmd_addr[11:10] :
(sdtype==2'b01)? cmd_addr[11:10] :
cmd_addr[10: 9] ;
wire[12:0] row_addr =
(sdtype==2'b11)? cmd_addr[25:13] :
(sdtype==2'b10)? cmd_addr[24:12] :
(sdtype==2'b01)? {1'b0, cmd_addr[23:12]} :
{1'b0, cmd_addr[22:11]} ;


///////////////////////////////////////////////////////
Expand All @@ -110,7 +137,8 @@ module tsdram(
if(reset==0) begin
ref_count <= tPOR_count[15:0];
end else if(ref_ack) begin
ref_count <= tREF_count[15:0];
// ref_count <= tREF_count[15:0];
ref_count <= {6'b0, reg_sdram[9:0]};
end else if(ref_count) begin
ref_count <= ref_count-1'b1;
end
Expand Down
44 changes: 36 additions & 8 deletions Firm_MCU/Main/main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -244,25 +244,53 @@ int flash_update(int check)
_puts("erase ...\n");
retv = flash_erase(firm_addr);
if(retv){
restore_irq(key);
_puts(" faile!\n");
return -2;
retv = -2;
goto _exit;
}

_puts("write ...\n");
for(i=0; i<fsize; i+=32){
retv = flash_write32(firm_addr+i, fbuf+i);
if(retv){
restore_irq(key);
_puts(" faile!\n");
return -3;
retv = -3;
goto _exit;
}
}

_exit:
if(retv){
_puts(" faile!\n");
}
*(volatile u16*)(0x60000012) = retv;
*(volatile u16*)(0x60000010) = 0;

restore_irq(key);

printk("MCU update OK!\n");
f_unlink("/SAROO/update/ssmaster.bin");
if(retv==0){
_puts("MCU update OK!\n");
f_unlink("/SAROO/update/ssmaster.bin");
}

return retv;
}


int flash_write_config(u8 *cfgbuf)
{
int retv;

retv = flash_erase(0x080e0000);
if(retv){
printk("erase failed! %08x\n", retv);
return retv;
}

retv = flash_write32(0x080e0000, cfgbuf);
if(retv){
printk("write failed! %08x\n", retv);
return retv;
}

return 0;
}

Expand Down
15 changes: 15 additions & 0 deletions Firm_MCU/Main/shell.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -296,6 +296,17 @@ void simple_shell(void)
CMD(flu){
flash_update(0);
}
CMD(sdram){
void sdram_config(int type, int reftime);
int type=3, reftime=64;
if(argc>=1){
type = arg[0];
}
if(argc>=2){
reftime = arg[1];
}
sdram_config(type, reftime);
}

CMD(mmt){
u32 addr = 0x61000000;
Expand Down Expand Up @@ -378,6 +389,10 @@ void simple_shell(void)
printk("create exram.bin failed! %d\n", retv);
}
}
CMD(pt){
void show_pt(int id);
show_pt(arg[0]);
}

CMD(q){
break;
Expand Down
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