Implementation of "Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks." 2021 58th ACM/IEEE Design Automation Conference (DAC).
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Feb 8, 2023 - Python
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stuck-at-faults
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Generation of test pattern or input vector for a given circuit consisting of stuck-at faults and to also determine the expected output. Submitted as part of the Grand Finale of Google Girl Hackathon 2023.
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Jul 14, 2023 - C++
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
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May 28, 2024 - Verilog
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
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Dec 24, 2024 - Verilog
Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).
testing dft eda gsoc design-for-testability atpg fault-simulation vlsi-design path-oriented stuck-at-faults podem gsoc-2024
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Sep 30, 2024 - Python
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