Verilog Implementation of an ARM LEGv8 CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Implemented a multi-cycle CPU with 54 MIPS instructions and CP0 coprocessor using Verilog language at the behavioral level. The design supports interrupts.

MIPS CPU constructed in verilog

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

It's a simple verilog based MIPS microarchitecture hardware design.

Computer Architecture I (University of Aveiro)

Single-cycle and multi-cycle implementation of a subset of MIPS instruction set

Single-cycle and multi-cycle verilog implementation of a subset of MIPS instruction set

Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier.

Projects of the computer architecture course (Fall01) at the University of Tehran.

MIPS processor designed in Verilog.