A High-performance Timing Analysis Tool for VLSI Systems
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Updated
May 26, 2023 - Verilog
A High-performance Timing Analysis Tool for VLSI Systems
A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)
[NeurIPS 2024] ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolution
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
A Standalone Structural Verilog Parser
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
VLSI EDA Global Router
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
Awesome machine learning for logic synthesis
This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.
A standalone structural (gate-level) verilog parser
RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).
Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!
the awesome work, project and lab of EDA (Electronic Design Automation). continue update...
This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.
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