rename the generated signature file to be of a similar format to the

reference file <stub>.reference_output <stub>.signature_output add missing reference signature file for rv32ui/srli change verify.sh to perform a backward link check
tjaychen · Nov 13, 2018 · 797ce6c · 797ce6c
1 parent a4247f7
commit 797ce6c
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diff --git a/doc/README.adoc b/doc/README.adoc
@@ -420,8 +420,8 @@ codasip_signature_end:
 For example, to support the Codasip ISA simulator as the device under test
 (DUT), it was necessary to change `RISCV_SIM` from `spike` to
 `codix_berkelium-ia-isimulator –r` and parameters for running the simulator
-from `+signature=$(work_dir)/$<_signature.output` to `–info 5` plus handle
-redirection to a file by `1>$(work_dir)/$<_signature.output`.
+from `+signature=$(work_dir)/$<.signature.output` to `–info 5` plus handle
+redirection to a file by `1>$(work_dir)/$<.signature.output`.
 
 == Configuring the target device
 
@@ -437,7 +437,7 @@ For example for the riscvOVPsim to be configured to be a RV32I
 RUN_TARGET= \
         riscvOVPsim.exe --variant RV32I --program $(work_dir_isa)/$< \
             --signaturedump \
-            --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+            --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
             --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
             --override riscvOVPsim/cpu/simulateexceptions=T \
             --logfile $(work_dir_isa)/$@

diff --git a/riscv-target/Codasip-simulator/device/rv32i/Makefile.include b/riscv-target/Codasip-simulator/device/rv32i/Makefile.include
@@ -7,8 +7,8 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) -r --info 5 \
-    $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 1>$(work_dir_isa)/$(*)_signature.output
-#        +signature=$(work_dir_isa)/$(*)_signature.output \
+    $(work_dir_isa)/$< 2> $(work_dir_isa)/$@ 1>$(work_dir_isa)/$(*).signature.output
+#        +signature=$(work_dir_isa)/$(*).signature.output \
 #        $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= codix_berkelium-ia-

diff --git a/riscv-target/riscvOVPsim/device/rv32i/Makefile.include b/riscv-target/riscvOVPsim/device/rv32i/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32I --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32im/Makefile.include b/riscv-target/riscvOVPsim/device/rv32im/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32IM --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32imc/Makefile.include b/riscv-target/riscvOVPsim/device/rv32imc/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32IMC --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32mi/Makefile.include b/riscv-target/riscvOVPsim/device/rv32mi/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32I --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32si/Makefile.include b/riscv-target/riscvOVPsim/device/rv32si/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32I --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32ua/Makefile.include b/riscv-target/riscvOVPsim/device/rv32ua/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32IMAC --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32uc/Makefile.include b/riscv-target/riscvOVPsim/device/rv32uc/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32IMC --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32ud/Makefile.include b/riscv-target/riscvOVPsim/device/rv32ud/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32G --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32uf/Makefile.include b/riscv-target/riscvOVPsim/device/rv32uf/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32G --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv32ui/Makefile.include b/riscv-target/riscvOVPsim/device/rv32ui/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV32I --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv64i/Makefile.include b/riscv-target/riscvOVPsim/device/rv64i/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV64I --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/riscvOVPsim/device/rv64im/Makefile.include b/riscv-target/riscvOVPsim/device/rv64im/Makefile.include
@@ -13,7 +13,7 @@ RUN_TARGET=\
     $(TARGET_SIM) \
         --variant RV64IM --program $(work_dir_isa)/$< \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \

diff --git a/riscv-target/spike/device/rv32i/Makefile.include b/riscv-target/spike/device/rv32i/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32i \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32im/Makefile.include b/riscv-target/spike/device/rv32im/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32im \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32imc/Makefile.include b/riscv-target/spike/device/rv32imc/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32imc \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32mi/Makefile.include b/riscv-target/spike/device/rv32mi/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32i \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32si/Makefile.include b/riscv-target/spike/device/rv32si/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32i \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32ua/Makefile.include b/riscv-target/spike/device/rv32ua/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) -l --isa=rv32imac \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32uc/Makefile.include b/riscv-target/spike/device/rv32uc/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32imc \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32ud/Makefile.include b/riscv-target/spike/device/rv32ud/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32g \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32uf/Makefile.include b/riscv-target/spike/device/rv32uf/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32g \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv32ui/Makefile.include b/riscv-target/spike/device/rv32ui/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv32i \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv64i/Makefile.include b/riscv-target/spike/device/rv64i/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv64i \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-target/spike/device/rv64im/Makefile.include b/riscv-target/spike/device/rv64im/Makefile.include
@@ -5,7 +5,7 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) --isa=rv64im \
-        +signature=$(work_dir_isa)/$(*)_signature.output \
+        +signature=$(work_dir_isa)/$(*).signature.output \
         $(work_dir_isa)/$< 2> $(work_dir_isa)/$@
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-

diff --git a/riscv-test-env/verify.sh b/riscv-test-env/verify.sh
@@ -4,22 +4,24 @@ printf "\n\nCompare to reference files ... \n\n";
 FAIL=0
 RUN=0
 
-for f in ${SUITEDIR}/references/*.reference_output;
+for ref in ${SUITEDIR}/references/*.reference_output;
 do 
-    b=$(basename $f)
-    ex=${b//".reference_output"/}
+    base=$(basename ${ref})
+    stub=${base//".reference_output"/}
+    sig=${WORK}/${RISCV_ISA}/${stub}.signature.output
+
     RUN=$((${RUN} + 1))
 
     #
     # Ensure both files exist
     #
-    if [ -f $f ] && [ -f ${WORK}/${ISA}/${b//".reference_output"/"_signature.output"} ]; then 
-        echo -n "Check $(printf %16s ${ex})"
+    if [ -f ${ref} ] && [ -f ${sig} ]; then 
+        echo -n "Check $(printf %16s ${stub})"
     else
-        echo    "Check $(printf %16s ${ex}) ... IGNORE"
+        echo    "Check $(printf %16s ${stub}) ... IGNORE"
         continue
     fi
-    diff --strip-trailing-cr $f ${WORK}/${ISA}/${b//".reference_output"/"_signature.output"} #&> /dev/null
+    diff --strip-trailing-cr ${ref} ${sig} #&> /dev/null
     if [ $? == 0 ]
     then
         echo " ... OK"
@@ -29,6 +31,19 @@ do
     fi
 done
 
+# warn on missing reverse reference
+for sig in ${WORK}/${RISCV_ISA}/*.signature.output; 
+do
+    base=$(basename ${sig})
+    stub=${base//".signature.output"/}
+    ref=${SUITEDIR}/references/${stub}.reference_output
+
+    if [ -f $sig ] && [ ! -f ${ref} ]; then
+        echo "Error: sig ${sig} no corresponding ${ref}"
+        FAIL=$((${FAIL} + 1))
+    fi
+done
+
 declare -i status=0
 if [ ${FAIL} == 0 ]
 then

diff --git a/riscv-test-suite/rv32i/Makefile b/riscv-test-suite/rv32i/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32im/Makefile b/riscv-test-suite/rv32im/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32imc/Makefile b/riscv-test-suite/rv32imc/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32mi/Makefile b/riscv-test-suite/rv32mi/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32si/Makefile b/riscv-test-suite/rv32si/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32ua/Makefile b/riscv-test-suite/rv32ua/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32uc/Makefile b/riscv-test-suite/rv32uc/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32ud/Makefile b/riscv-test-suite/rv32ud/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32uf/Makefile b/riscv-test-suite/rv32uf/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 

diff --git a/riscv-test-suite/rv32ui/Makefile b/riscv-test-suite/rv32ui/Makefile
@@ -5,7 +5,7 @@
 act_dir := .
 src_dir := $(act_dir)/src
 work_dir := $(ROOTDIR)/work
-work_dir_isa := $(work_dir)/$(ISA)
+work_dir_isa := $(work_dir)/$(RISCV_ISA)
 
 include $(act_dir)/Makefrag
 
@@ -48,6 +48,7 @@ $(eval $(call compile_template,rv32ui,-march=rv32i -mabi=ilp32))
 tests32_out = $(patsubst %.elf,%.out32,$(target32_tests))
 
 run: $(tests32_out)
+	echo "+++ $^ +++"
 
 #------------------------------------------------------------
 # Default