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Improved test coverage
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moore committed Sep 13, 2018
1 parent 9273836 commit 53c8bd6
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6 changes: 6 additions & 0 deletions ChangeLog
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@@ -1,3 +1,9 @@
2018-09-10 Lee Moore <[email protected]>
* Added tests to improve coverage, usage of Imperas Mutating Fault Simulator to
identify untested usage cases
* macro renames to support GPR, (S)FPR, (D)FPR


2018-06-15 Radek Hajek <[email protected]>

Modifications to support Codasip simulator.
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4 changes: 2 additions & 2 deletions doc/README.adoc
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Expand Up @@ -274,7 +274,7 @@ This description assumes the use of a configurable simulator with good trace and

* Ensure that the processor configuration is set appropriately.

* Use the `RVTEST` macros (defined in `compliance_io.h`) to make it easy to see the details of a Test’s execution. There are macros for assertions (`RVTEST_IO_ASSERT_EQ`) and tracing (`RVTEST_IO_WRITE_STR`) which are empty on targets that can not implement them.
* Use the `RVTEST` macros (defined in `compliance_io.h`) to make it easy to see the details of a Test’s execution. There are macros for assertions (`RVTEST_IO_ASSERT_GPR_EQ`) and tracing (`RVTEST_IO_WRITE_STR`) which are empty on targets that can not implement them.

* Assuming you are developing the test on a simulator, use the simulator’s tracing capabilities, especially a register change mode to single step your test examining all changing registers etc. to ensure your test is stimulating what is intending.

Expand Down Expand Up @@ -328,7 +328,7 @@ For tracing the test the following macros are defined in `riscv-target/riscvOVP
----
RVTEST_IO_INIT
RVTEST_IO_WRITE_STR(_STR)
RVTEST_IO_ASSERT_EQ(_R, _I)
RVTEST_IO_ASSERT_GPR_EQ(_R, _I)
----

An example of a test that uses the tracing macros is `riscv-test-suite/rv32i/ISA/src/I-IO.S`.
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2 changes: 1 addition & 1 deletion riscv-target/Codasip-simulator/compliance_io.h
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Expand Up @@ -15,6 +15,6 @@
#define RVTEST_IO_INIT
#define RVTEST_IO_PUTC(_R)
#define RVTEST_IO_WRITE_STR(_STR)
#define RVTEST_IO_ASSERT_EQ(_R, _I)
#define RVTEST_IO_ASSERT_GPR_EQ(_R, _I)

#endif // _COMPLIANCE_IO_H
82 changes: 42 additions & 40 deletions riscv-target/riscvOVPsim/compliance_io.h
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Expand Up @@ -28,7 +28,7 @@
#ifndef _COMPLIANCE_IO_H
#define _COMPLIANCE_IO_H

//#define RVTEST_IO_QUIET
#define RVTEST_IO_QUIET

//-----------------------------------------------------------------------
// RV IO Macros (Character transfer by custom instruction)
Expand All @@ -43,16 +43,35 @@
#define RVTEST_IO_INIT
#define RVTEST_IO_WRITE_STR(_STR)
#define RVTEST_IO_CHECK()
#define LOCAL_IO_PUTC(_R)
#define RVTEST_IO_ASSERT_EQ(_R, _I)
#define RVTEST_FP_ASSERT_EQ(_F, _C, correctval)
#define RVTEST_FP2_ASSERT_EQ(_F, _C, correctval)
#define RVTEST_FPD_ASSERT_EQ(_F, _C, correctval)
#define RVTEST_IO_ASSERT_GPR_EQ(_R, _I)
#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)

#else

#define LOCAL_IO_WRITE_GPR(_R) \
mv a0, _R; \
jal FN_WriteA0;

#define LOCAL_IO_WRITE_FPR(_F) \
fmv.x.s a0, _F; \
jal FN_WriteA0;

#define LOCAL_FPD_WRITE_REG(_V1, _V2) \
mv a0, _V1; \
jal FN_WriteA0; \
mv a0, _V2; \
jal FN_WriteA0; \

#define LOCAL_IO_PUTC(_R) \
.word RVTEST_CUSTOM1; \

#define RVTEST_IO_INIT

// Assertion violation: file file.c, line 1234: (expr)
#define RVTEST_IO_ASSERT_EQ(_R, _I) \
// _R = GPR
// _I = Immediate
#define RVTEST_IO_ASSERT_GPR_EQ(_R, _I) \
li t0, _I; \
beq _R, t0, 20002f; \
RVTEST_IO_WRITE_STR("Assertion violation: file "); \
Expand All @@ -62,15 +81,18 @@
RVTEST_IO_WRITE_STR(": "); \
RVTEST_IO_WRITE_STR(# _R); \
RVTEST_IO_WRITE_STR("("); \
LOCAL_IO_WRITE_REG(_R); \
LOCAL_IO_WRITE_GPR(_R); \
RVTEST_IO_WRITE_STR(") != "); \
RVTEST_IO_WRITE_STR(# _I); \
RVTEST_IO_WRITE_STR("\n"); \
li TESTNUM, 100; \
RVTEST_FAIL; \
20002:

#define RVTEST_FP_ASSERT_EQ(_F, _C, correctval) \
// _F = FPR
// _C = GPR
// _I = Immediate
#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _C, _I) \
fmv.x.s t0, _F; \
beq _C, t0, 20003f; \
RVTEST_IO_WRITE_STR("Assertion violation: file "); \
Expand All @@ -80,55 +102,35 @@
RVTEST_IO_WRITE_STR(": "); \
RVTEST_IO_WRITE_STR(# _F); \
RVTEST_IO_WRITE_STR("("); \
LOCAL_FP_WRITE_REG(_F); \
LOCAL_IO_WRITE_FPR(_F); \
RVTEST_IO_WRITE_STR(") != "); \
RVTEST_IO_WRITE_STR(# correctval); \
RVTEST_IO_WRITE_STR(# _I); \
RVTEST_IO_WRITE_STR("\n"); \
li TESTNUM, 100; \
RVTEST_FAIL; \
20003:

#define RVTEST_FP2_ASSERT_EQ(_F, _C, correctval) \
mv t0, _F; \
beq _C, t0, 20004f; \
RVTEST_IO_WRITE_STR("Assertion violation: file "); \
RVTEST_IO_WRITE_STR(__FILE__); \
RVTEST_IO_WRITE_STR(", line "); \
RVTEST_IO_WRITE_STR(TOSTRING(__LINE__)); \
RVTEST_IO_WRITE_STR(": "); \
RVTEST_IO_WRITE_STR(# _F); \
RVTEST_IO_WRITE_STR("("); \
LOCAL_IO_WRITE_REG(_F); \
RVTEST_IO_WRITE_STR(") != "); \
RVTEST_IO_WRITE_STR(# correctval); \
RVTEST_IO_WRITE_STR("\n"); \
li TESTNUM, 100; \
RVTEST_FAIL; \
20004:

#define RVTEST_FPD_ASSERT_EQ(_F, _C, correctval) \
fmv.x.d t0, _F; \
beq _C, t0, 20005f; \
// _D = DFPR
// _R = GPR
// _I = Immediate
#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) \
fmv.x.d t0, _D; \
beq _R, t0, 20005f; \
RVTEST_IO_WRITE_STR("Assertion violation: file "); \
RVTEST_IO_WRITE_STR(__FILE__); \
RVTEST_IO_WRITE_STR(", line "); \
RVTEST_IO_WRITE_STR(TOSTRING(__LINE__)); \
RVTEST_IO_WRITE_STR(": "); \
RVTEST_IO_WRITE_STR(# _F); \
RVTEST_IO_WRITE_STR(# _D); \
RVTEST_IO_WRITE_STR("("); \
LOCAL_FPD_WRITE_REG(_F); \
LOCAL_FPD_WRITE_REG(_D); \
RVTEST_IO_WRITE_STR(") != "); \
RVTEST_IO_WRITE_STR(# correctval); \
RVTEST_IO_WRITE_STR(# _I); \
RVTEST_IO_WRITE_STR("\n"); \
li TESTNUM, 100; \
RVTEST_FAIL; \
20005:

#define LOCAL_IO_PUTC(_R) \
.word RVTEST_CUSTOM1; \

#define RVTEST_IO_INIT

#define RVTEST_IO_WRITE_STR(_STR) \
.section .data.string; \
20001: \
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1 change: 1 addition & 0 deletions riscv-target/riscvOVPsim/device/rv32im/Makefile.include
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Expand Up @@ -16,6 +16,7 @@ RUN_TARGET=\
--override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*)_signature.output \
--override riscvOVPsim/cpu/sigdump/ResultReg=3 \
--override riscvOVPsim/cpu/simulateexceptions=T \
--override riscvOVPsim/cpu/defaultsemihost=F \
--logfile $(work_dir_isa)/$@ \
--override riscvOVPsim/cpu/user_version=2.3 \
--override riscvOVPsim/cpu/priv_version=1.11 \
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10 changes: 4 additions & 6 deletions riscv-target/spike/compliance_io.h
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Expand Up @@ -29,10 +29,8 @@
#define RVTEST_IO_INIT
#define RVTEST_IO_WRITE_STR(_STR)
#define RVTEST_IO_CHECK()
#define LOCAL_IO_PUTC(_R)
#define RVTEST_IO_ASSERT_EQ(_R, _I)
#define RVTEST_FP_ASSERT_EQ(_F, _C, correctval)
#define RVTEST_FP2_ASSERT_EQ(_F, _C, correctval)
#define RVTEST_FPD_ASSERT_EQ(_F, _C, correctval)
#define RVTEST_IO_ASSERT_GPR_EQ(_R, _I)
#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)

#endif // _COMPLIANCE_IO_H
#endif // _COMPLIANCE_IO_H
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