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updated rv32i tests to support all registers (x31) with assertions
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updated spec/TestFormatSpec.adoc example ISA test with new assertions
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@jeremybennett
Codasip authored and jeremybennett committed Feb 15, 2019
1 parent 90ed5f0 commit 2c84277
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4 changes: 4 additions & 0 deletions ChangeLog
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@@ -1,3 +1,7 @@
2019-02-15 Radek Hajek <[email protected]>
* updated rv32i tests to support all registers (x31) with assertions
* updated spec/TestFormatSpec.adoc example ISA test with new assertions

2019-02-05 Deborah Soung <[email protected]>
* [Issue #33] fixing rv32si/ma_fetch.S test

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4 changes: 2 additions & 2 deletions riscv-test-suite/README.md
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Expand Up @@ -11,8 +11,8 @@ If you are looking to check compliance of RV32I in user mode then run the suites
Test suites status:

Pretty Solid:
* RV32I (originally developed by Codasip, updated significantly by Imperas to improve coverage)
* 54 focused tests, using the correct style/macros, excellent coverage of most instructions
* RV32I (originally developed by Codasip, assertions and debug macros added by Imperas)
* 55 focused tests, using the correct style/macros, excellent coverage of most instructions
* no coverage of fence, scall, sbreak, pseudo and csr instructions
* RV32IM (developed by Imperas)
* 7 focused tests, using the correct style/macros, excellent coverage
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i/references/I-NOP-01.reference_output
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Expand Up @@ -28,5 +28,5 @@
0000001c
0000001d
0000001e
ffffffff
0000001f
00000018
2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i/references/I-RF_size-01.reference_output
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Expand Up @@ -29,7 +29,7 @@
3a290d0a
68697320
61642074
ffffffff
75207265
00000000
56333249
2d562052
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i/references/I-RF_width-01.reference_output
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Expand Up @@ -29,4 +29,4 @@
80000000
80000000
80000000
ffffffff
80000000
96 changes: 48 additions & 48 deletions riscv-test-suite/rv32i/src/I-ADD-01.S
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Expand Up @@ -41,7 +41,7 @@ RV_COMPLIANCE_CODE_BEGIN

RVTEST_IO_INIT
RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
RVTEST_IO_WRITE_STR(x31, "# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")

# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n");
Expand Down Expand Up @@ -79,12 +79,12 @@ RV_COMPLIANCE_CODE_BEGIN
// Assert
//
RVTEST_IO_CHECK()
RVTEST_IO_ASSERT_GPR_EQ(x31, x3, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x4, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x5, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x6, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x7, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x8, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000)

RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n");

Expand Down Expand Up @@ -120,12 +120,12 @@ RV_COMPLIANCE_CODE_BEGIN
sw x12, 16(x2)
sw x13, 20(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x8, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x31, x9, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x31, x10, 0x00000002)
RVTEST_IO_ASSERT_GPR_EQ(x31, x11, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x12, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x13, 0x80000001)
RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000002)
RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x80000001)

RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n");

Expand Down Expand Up @@ -161,12 +161,12 @@ RV_COMPLIANCE_CODE_BEGIN
sw x17, 16(x2)
sw x18, 20(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x13, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x14, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x15, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x16, 0xFFFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x17, 0x7FFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x18, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x7FFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF)

RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n");

Expand Down Expand Up @@ -202,12 +202,12 @@ RV_COMPLIANCE_CODE_BEGIN
sw x22, 16(x2)
sw x23, 20(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x18, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x19, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x20, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x21, 0x7FFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x22, 0xFFFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x23, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x7FFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0xFFFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xFFFFFFFF)

RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n");

Expand Down Expand Up @@ -243,12 +243,12 @@ RV_COMPLIANCE_CODE_BEGIN
sw x27, 16(x2)
sw x28, 20(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x23, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x24, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x25, 0x80000001)
RVTEST_IO_ASSERT_GPR_EQ(x31, x26, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x27, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x28, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x80000001)
RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000000)

RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n");

Expand All @@ -268,8 +268,8 @@ RV_COMPLIANCE_CODE_BEGIN
# Test
add x29, x28, x27
add x30, x29, x27
add x21, x30, x27
add x1, x21, x27
add x31, x30, x27
add x1, x31, x27
add x2, x1, x27
add x3, x2, x27

Expand All @@ -278,19 +278,19 @@ RV_COMPLIANCE_CODE_BEGIN
sw x28, 4(x26)
sw x29, 8(x26)
sw x30, 12(x26)
sw x21, 16(x26)
sw x31, 16(x26)
sw x1, 20(x26)
sw x2, 24(x26)
sw x3, 28(x26)

RVTEST_IO_ASSERT_GPR_EQ(x31, x27, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x31, x28, 0x0000ABCD)
RVTEST_IO_ASSERT_GPR_EQ(x31, x29, 0x0000ABCE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x30, 0x0000ABCF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x21, 0x0000ABD0)
RVTEST_IO_ASSERT_GPR_EQ(x31, x1, 0x0000ABD1)
RVTEST_IO_ASSERT_GPR_EQ(x31, x2, 0x0000ABD2)
RVTEST_IO_ASSERT_GPR_EQ(x31, x3, 0x0000ABD3)
RVTEST_IO_ASSERT_GPR_EQ(x26, x27, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0x0000ABCD)
RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0x0000ABCE)
RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0x0000ABCF)
RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0x0000ABD0)
RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0x0000ABD1)
RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0x0000ABD2)
RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0x0000ABD3)

RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n");

Expand All @@ -313,7 +313,7 @@ RV_COMPLIANCE_CODE_BEGIN
# store results
sw x0, 0(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000)

RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n");

Expand All @@ -339,8 +339,8 @@ RV_COMPLIANCE_CODE_BEGIN
sw x5, 4(x2)


RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x5, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000)

RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n");

Expand Down Expand Up @@ -370,9 +370,9 @@ RV_COMPLIANCE_CODE_BEGIN
sw x26, 4(x2)
sw x27, 8(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x4, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x31, x26, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x31, x27, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814)

RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n");

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96 changes: 48 additions & 48 deletions riscv-test-suite/rv32i/src/I-ADDI-01.S
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ RV_COMPLIANCE_CODE_BEGIN

RVTEST_IO_INIT
RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
RVTEST_IO_WRITE_STR(x31, "# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")

# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n");
Expand Down Expand Up @@ -72,12 +72,12 @@ RV_COMPLIANCE_CODE_BEGIN
// Assert
//
RVTEST_IO_CHECK()
RVTEST_IO_ASSERT_GPR_EQ(x31, x3, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x4, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x31, x5, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x6, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x7, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x8, 0xFFFFF800)
RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0xFFFFF800)

RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n");

Expand Down Expand Up @@ -106,12 +106,12 @@ RV_COMPLIANCE_CODE_BEGIN
sw x12, 16(x2)
sw x13, 20(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x8, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x31, x9, 0x00000002)
RVTEST_IO_ASSERT_GPR_EQ(x31, x10, 0x00000800)
RVTEST_IO_ASSERT_GPR_EQ(x31, x11, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x12, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x31, x13, 0xFFFFF801)
RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000002)
RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000800)
RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001)
RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFF801)

RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n");

Expand Down Expand Up @@ -140,12 +140,12 @@ RV_COMPLIANCE_CODE_BEGIN
sw x17, 16(x2)
sw x18, 20(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x13, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x14, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x15, 0x000007FE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x16, 0xFFFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x17, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x18, 0xFFFFF7FF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x000007FE)
RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFFF7FF)

RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n");

Expand Down Expand Up @@ -174,12 +174,12 @@ RV_COMPLIANCE_CODE_BEGIN
sw x22, 16(x2)
sw x23, 20(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x18, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x19, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x20, 0x800007FE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x21, 0x7FFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x22, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x23, 0x7FFFF7FF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x800007FE)
RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x7FFFFFFE)
RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x7FFFF7FF)

RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n");

Expand Down Expand Up @@ -208,12 +208,12 @@ RV_COMPLIANCE_CODE_BEGIN
sw x27, 16(x2)
sw x28, 20(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x23, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x24, 0x80000001)
RVTEST_IO_ASSERT_GPR_EQ(x31, x25, 0x800007FF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x26, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x27, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x28, 0x7FFFF800)
RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000001)
RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x800007FF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7FFFFFFF)
RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x80000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFF800)

RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n");

Expand All @@ -230,28 +230,28 @@ RV_COMPLIANCE_CODE_BEGIN
# Test
addi x29, x28, 1
addi x30, x29, 1
addi x21, x30, 1
addi x1, x21, 1
addi x31, x30, 1
addi x1, x31, 1
addi x2, x1, 1
addi x3, x2, 1

# Store results
sw x28, 0(x27)
sw x29, 4(x27)
sw x30, 8(x27)
sw x21, 12(x27)
sw x31, 12(x27)
sw x1, 16(x27)
sw x2, 20(x27)
sw x3, 24(x27)


RVTEST_IO_ASSERT_GPR_EQ(x31, x28, 0x0000ABCD)
RVTEST_IO_ASSERT_GPR_EQ(x31, x29, 0x0000ABCE)
RVTEST_IO_ASSERT_GPR_EQ(x31, x30, 0x0000ABCF)
RVTEST_IO_ASSERT_GPR_EQ(x31, x21, 0x0000ABD0)
RVTEST_IO_ASSERT_GPR_EQ(x31, x1, 0x0000ABD1)
RVTEST_IO_ASSERT_GPR_EQ(x31, x2, 0x0000ABD2)
RVTEST_IO_ASSERT_GPR_EQ(x31, x3, 0x0000ABD3)
RVTEST_IO_ASSERT_GPR_EQ(x27, x28, 0x0000ABCD)
RVTEST_IO_ASSERT_GPR_EQ(x27, x29, 0x0000ABCE)
RVTEST_IO_ASSERT_GPR_EQ(x27, x30, 0x0000ABCF)
RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x0000ABD0)
RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0x0000ABD1)
RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0x0000ABD2)
RVTEST_IO_ASSERT_GPR_EQ(x27, x3, 0x0000ABD3)

RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n");

Expand All @@ -271,7 +271,7 @@ RV_COMPLIANCE_CODE_BEGIN
# Store results
sw x0, 0(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000)

RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n");

Expand All @@ -293,8 +293,8 @@ RV_COMPLIANCE_CODE_BEGIN
sw x0, 0(x2)
sw x5, 4(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x31, x5, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000)
RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000)

RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n");

Expand Down Expand Up @@ -325,10 +325,10 @@ RV_COMPLIANCE_CODE_BEGIN
sw x26, 8(x2)
sw x27, 12(x2)

RVTEST_IO_ASSERT_GPR_EQ(x31, x3, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x31, x4, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x31, x26, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x31, x27, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814)
RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814)

RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n");

Expand Down
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