VILLASfpga cosimulation development #325
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n-eiling
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m-mirz,
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dinkelbachjan
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stv0g
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@n-eiling Quick nit: please make sure to use the correct capitalization of "VILLASfpga" (see title) |
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VILLASfpga does not exist anymore. I thought about VILLASnode nodetype fpga :) |
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The CI is failing because of missing pybind interfaces. I'll try to fix it in the next days - but the rest should not change anymore. |
adds a new data logger interface for simulation result logging. Besides the existing DataLogger, the interface is implemented by the new RealTimeDataLogger that preallocates a buffer for the results and only writes them after the simulation finished. This does not break existing code. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
This adds FpgaCosimulation.cpp, an example for a cosimulation with another simulator running a WSCC 9 bus and DPsim running the load connected to bus 5. This also modifies EMT::Ph3::RXLoad to allow it to represent an R-L series load rather than only a parallel load. It also adds EMT::Ph3::ControlledVoltageSource, a voltage source with EMT setpoints for feeding interface data into the DPsim simulation. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
…PHIL and co-simulation Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
…ake simulation more stable Signed-off-by: Niklas Eiling <[email protected]>
…iles. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
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Signed-off-by: Niklas Eiling <[email protected]>
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This writes simulation results to memory and only dumps to a file when the simulation ends. It allocates a buffer that is attributes*simulation duration/time step long - so this only works for relatively short simulations.
EMT::Ph3::ControlledVoltageSourceandEMT::Ph3::ControlledCurrentSource. The existing sourcesEMT::Ph3::VoltageSourceandEMT::Ph3::CurrentSourceonly allow setting RMS voltages and derives the individual phase voltages from that. This cannot be used for PHIL or Co-Simulations where we need the set each phase voltage individually. The existing voltage source can also not be easily adapted to support both, so I created a new model (RTDS and Simulink also have a separate model for this so it makes sense).EMT::Ph3::RXLoadto be able to implement a series R-L load instead of only a parallel R-L load. The series load is needed for the WSCC 9 bus model.FPGACosimulation, an example of using dpsim-villas to build a co-simulation where DPsim simulates load connected to bus 5 in a WSCC 9 bus model.FPGACosim3PhInfiniteBus, an example that implements an infinite bus to be connected with a load in another simulator.