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Working model #1

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shambhavii13 May 6, 2023
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156 changes: 156 additions & 0 deletions ALU.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALU is
port(ALU_A , ALU_B : in std_logic_vector(15 downto 0); ALU_OP : in std_logic_vector(3 downto 0); ALU_C : out std_logic_vector(15 downto 0);
ALU_Z, ALU_C1 : in std_logic; ALU_Carry, ALU_Zero : out std_logic; clk : in std_logic);
end entity ALU;

architecture Structure_ALU of ALU is

function NAND_16(A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable result : std_logic_vector(15 downto 0) := (others => '0');
begin
L1 : for i in 0 to 15 loop
result(i) := A(i) nand B(i);
end loop L1;
return result;
end function NAND_16;
--------------------------------------------------------------------------------------------------------------------------------
function ADD_16(A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0)) return std_logic_vector is
variable C : std_logic_vector(16 downto 0) := (others => '0');
variable S : std_logic_vector(15 downto 0);
begin
Loop1: for i in 0 to 15 loop
S(i) := A(i) xor B(i) xor C(i);
C(i+1) := ( A(i) and C(i) ) or ( ( A(i) xor C(i) ) and B(i) );
end loop Loop1;
return S & C(16);
end function ADD_16;
---------------------------------------------------------------------------------------------------------------------------------
function AWC_16(A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0); Carry : in std_logic) return std_logic_vector is
variable C : std_logic_vector(16 downto 0) := ( 0 => Carry , others => '0');
variable S : std_logic_vector(15 downto 0);
begin
Loop1: for i in 0 to 15 loop
S(i) := A(i) xor B(i) xor C(i);
C(i+1) := ( A(i) and C(i) ) or ( ( A(i) xor C(i) ) and B(i) );
end loop Loop1;
return S & C(16);
end function AWC_16;
--------------------------------------------------------------------------------------------------------------------------------
function LMSM(A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0)) return std_logic_vector is
begin
Loop1: for i in 0 to 15 loop
if B(i) = '1' then
return std_logic_vector( to_unsigned( (to_integer(unsigned(A)) + i) , 16) );
end if;
end loop Loop1;
return A;
end function LMSM;
------------------------------------------------------------------------------------------------------------------------
signal add16_out : std_logic_vector(16 downto 0);
signal add16_c_out : std_logic_vector(16 downto 0);
signal awc16_out : std_logic_vector(16 downto 0);
signal awc16_c_out : std_logic_vector(16 downto 0);
begin
ALU_Process : process(ALU_A, ALU_B, ALU_OP, clk)
begin
-- if rising_edge(clk) then
if ALU_OP = "0000" then --ADD
add16_out <= ADD_16(ALU_A, ALU_B);
ALU_C <= add16_out(16 downto 1);
ALU_Carry <= add16_out(0);
if add16_out(16 downto 1) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_OP = "0001" then --Add with Carry
awc16_out <= AWC_16(ALU_A, ALU_B, ALU_C1);
ALU_C <= awc16_out(16 downto 1);
ALU_Carry <= awc16_out(0);
if awc16_out(16 downto 1) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_OP = "0010" then -- Add with Complement
add16_c_out <= ADD_16(ALU_A, not(ALU_B));
ALU_C <= add16_out(16 downto 1);
ALU_Carry <= add16_out(0);
if add16_c_out(16 downto 1) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_OP = "0011" then -- Add with complement and carry
awc16_c_out <= AWC_16(ALU_A, not(ALU_B), ALU_C1);
ALU_C <= awc16_c_out(16 downto 1);
ALU_Carry <= awc16_c_out(0);
if awc16_c_out(16 downto 1) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_OP = "0100" then --NAND
ALU_C <= NAND_16(ALU_A, ALU_B);
ALU_Carry <= ALU_C1;
if NAND_16(ALU_A, ALU_B) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_OP = "0101" then --NCU
ALU_C <= NAND_16(ALU_A, not(ALU_B));
ALU_Carry <= ALU_C1;
if NAND_16(ALU_A, not(ALU_B)) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_OP = "0110" then --BEQ
if ALU_A = ALU_B then
ALU_C <= "0000000000000001";
else
ALU_C <= "0000000000000000";
end if;
ALU_Carry <= ALU_C1;
ALU_Zero <= ALU_Z;
elsif ALU_OP = "0111" then --BLT
if ALU_A < ALU_B then
ALU_C <= "0000000000000001";
else
ALU_C <= "0000000000000000";
end if;
ALU_Carry <= ALU_C1;
ALU_Zero <= ALU_Z;
elsif ALU_OP = "1000" then --BLE
if ALU_A <= ALU_B then
ALU_C <= "0000000000000001";
else
ALU_C <= "0000000000000000";
end if;
ALU_Carry <= ALU_C1;
ALU_Zero <= ALU_Z;
elsif ALU_OP = "1110" then --LMSM
ALU_ZERO <= ALU_Z;
ALU_Carry <= ALU_C1;
ALU_C <= LMSM(ALU_A, ALU_B);
elsif ALU_OP = "1001" then --LLI
ALU_ZERO <= ALU_Z;
ALU_Carry <= ALU_C1;
ALU_C <= ALU_B;
else --others
ALU_ZERO <= ALU_Z;
ALU_Carry <= ALU_C1;
ALU_C <= "0000000000000000";
end if;
-- else
-- null;
-- end if;
end process ALU_Process;
end architecture Structure_ALU;
97 changes: 97 additions & 0 deletions ALU.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALU is
port (ALU_A , ALU_B : in std_logic_vector(15 downto 0); ALU_S : in std_logic_vector(3 downto 0); ALU_C : out std_logic_vector(15 downto 0);
ALU_Carry, ALU_Zero : out std_logic);
end entity ALU;

architecture Structure_ALU of ALU is

function NAND_16(A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable result : std_logic_vector(15 downto 0) := (others => '0');
begin
L1 : for i in 0 to 15 loop
result(i) := A(i) nand B(i);
end loop L1;
return result;
end function NAND_16;
--------------------------------------------------------------------------------------------------------------------------------
function ADD_16(A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0)) return std_logic_vector is
variable C : std_logic_vector(16 downto 0) := (others => '0');
variable S : std_logic_vector(15 downto 0);
begin
Loop1: for i in 0 to 15 loop
S(i) := A(i) xor B(i) xor C(i);
C(i+1) := ( A(i) and C(i) ) or ( ( A(i) xor C(i) ) and B(i) );
end loop Loop1;
return S;
end function ADD_16;
---------------------------------------------------------------------------------------------------------------------------------
function Carry_16(A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0)) return std_logic is
variable C : std_logic_vector(16 downto 0) := (others => '0');
-- variable S : std_logic_vector(15 downto 0);
begin
Loop1: for i in 0 to 15 loop
-- S(i) := A(i) xor B(i) xor C(i);
C(i+1) := ( A(i) and C(i) ) or ( ( A(i) xor C(i) ) and B(i) );
end loop Loop1;
return C(16);
end function Carry_16;
---------------------------------------------------------------------------------------------------------------------------------
function XOR_16(A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable result : std_logic_vector(15 downto 0) := (others => '0');
begin
L1 : for i in 0 to 15 loop
result(i) := A(i) xor B(i);
end loop L1;
return result;
end function XOR_16;
---------------------------------------------------------------------------------------------------------------------------------
begin
ALU_Process : process(ALU_A, ALU_B, ALU_S)
begin
if ALU_S = "0000" OR ALU_S = "0001" then
ALU_C <= ADD_16(ALU_A, ALU_B);
ALU_Carry <= Carry_16(ALU_A, ALU_B);
if ADD_16(ALU_A, ALU_B) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_S = "0010" then
ALU_CARRY<='0';--carry enable zero so we dont care
ALU_C <= NAND_16(ALU_A, ALU_B);
if NAND_16(ALU_A, ALU_B) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_S = "0100" then
ALU_CARRY<='0';--carry enable will take care
ALU_C <= ADD_16(ALU_A, ALU_B);
if ADD_16(ALU_A, ALU_B) = "0000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
elsif ALU_S = "0101" or ALU_S = "0110" or ALU_S = "0111" then
ALU_ZERO<='0';--zero enable will take care
ALU_CARRY<='0';--carry enable will take care
ALU_C <= ADD_16(ALU_A, ALU_B);
elsif ALU_S = "1100" then
ALU_CARRY<='0';--carry enable will take care
ALU_ZERO<='0';--zero enable will take care
ALU_C <= XOR_16(ALU_A, ALU_B);
else
ALU_ZERO<='0';--zero enable will take care
ALU_CARRY<='0';--carry enable will take care
ALU_C <= "0000000000000000";
end if;
end process ALU_Process;
end architecture Structure_ALU;
30 changes: 30 additions & 0 deletions ALU23.vhd
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library ieee;
use ieee.std_logic_1164.all;

entity ALU23 is
port (
input1: in std_logic_vector(15 downto 0);
input2: in std_logic_vector(15 downto 0);
ALU_out: out std_logic_vector(15 downto 0)
);

end ALU23;

architecture arch of ALU23 is

function add(A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0)) return std_logic_vector is
variable C : std_logic_vector(16 downto 0) := (others => '0');
variable S : std_logic_vector(15 downto 0) := (others => '0');
begin
Loop1: for i in 0 to 15 loop
S(i) := A(i) xor B(i) xor C(i);
C(i+1) := ( A(i) and C(i) ) or ( ( A(i) xor C(i) ) and B(i) );
end loop Loop1;
return S;
end add;

begin

ALU_out <= add(input1,input2);

end arch;
29 changes: 29 additions & 0 deletions ALU23.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;

entity ALU23 is
port (
input1: in std_logic_vector(15 downto 0);
input2: in std_logic_vector(15 downto 0);
ALU_out: out std_logic_vector(15 downto 0)
);

end ALU23;

architecture arch of ALU23 is

function add(A : in std_logic_vector(15 downto 0); B : in std_logic_vector(15 downto 0)) return std_logic_vector(15 downto 0) is
variable C : std_logic_vector(16 downto 0) := (others => '0');
variable S : std_logic_vector(15 downto 0) := (others => '0');
begin
Loop1: for i in 0 to 15 loop
S(i) := A(i) xor B(i) xor C(i);
C(i+1) := ( A(i) and C(i) ) or ( ( A(i) xor C(i) ) and B(i) );
end loop Loop1;
return S;
end add;

begin
ALU_out <= add(input1,input2);

end arch;
34 changes: 34 additions & 0 deletions DUT.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity DUT is
port(input_vector: in std_logic_vector(0 downto 0);
output_vector: out std_logic_vector(130 downto 0));
end entity;

architecture DutWrap of DUT is
component CPU is
port(clk : in std_logic;
output_dummy: out std_logic;
Reg0,Reg1,Reg2,Reg3,Reg4,Reg5,Reg6,Reg7: out std_logic_vector(15 downto 0);
Current_Zero_OUT, Current_Carry_OUT: out std_logic
);
end component;

begin
add_instance: CPU
port map(
clk => input_vector(0),
output_dummy => output_vector(130),
Reg0=> output_vector(129 downto 114),
Reg1=> output_vector(113 downto 98),
Reg2=> output_vector(97 downto 82),
Reg3=> output_vector(81 downto 66),
Reg4=> output_vector(65 downto 50),
Reg5=> output_vector(49 downto 34),
Reg6=> output_vector(33 downto 18),
Reg7=> output_vector(17 downto 2),
Current_Zero_OUT => output_vector(1),
Current_Carry_OUT => output_vector(0)
);

end DutWrap;
34 changes: 34 additions & 0 deletions DUT.vhd.bak
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Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
library ieee;
use ieee.std_logic_1164.all;
entity DUT is
port(input_vector: in std_logic_vector(0 downto 0);
output_vector: out std_logic_vector(0 downto 0));
end entity;

architecture DutWrap of DUT is
component CPU is
port(clk : in std_logic;
output_dummy: out std_logic;
R0,R1,R2,R3,R4,R5,R6,R7: out std_logic_vector(15 downto 0);
Current_Zero_OUT, Current_Carry_OUT: out std_logic;
);
end component;

begin
add_instance: CPU
port map(
clk => input_vector(0),
output_dummy => output_vector(130),
R0=> output_vector(129 downto 114),
R1=> output_vector(113 downto 98),
R2=> output_vector(97 downto 82),
R3=> output_vector(81 downto 66),
R4=> output_vector(65 downto 50),
R5=> output_vector(49 downto 34),
R6=> output_vector(33 downto 18),
R7=> output_vector(17 downto 2),
Current_Zero_OUT => output_vector(1),
Current_Carry_OUT => output_vector(0)
);

end DutWrap;
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