Skip to content

Commit

Permalink
Move verilator calls to inside Haskell test program
Browse files Browse the repository at this point in the history
  • Loading branch information
satnam6502 committed Jun 4, 2024
1 parent 2d0f8fd commit 14a3f93
Show file tree
Hide file tree
Showing 3 changed files with 10 additions and 3 deletions.
3 changes: 1 addition & 2 deletions .github/workflows/lava-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,6 @@ jobs:
ghcup set ghc ${{ matrix.compilerVersion }}
ghc --version
ghcup install cabal 3.10.3.0
ls -a ~
cabal v2-update
sudo apt-get update
sudo apt-get install -y verilator
Expand All @@ -59,4 +58,4 @@ jobs:
run: |
cd source
cabal v2-test
verilator +1800-2017ext+sv verilator.vlt --binary --trace -Wall --top-module nandgate_sim nandgate.sv nandgate_sim.sv
6 changes: 6 additions & 0 deletions test-verilator/Main.hs
Original file line number Diff line number Diff line change
@@ -1,9 +1,15 @@
module Main (main) where

import Lava
import System.Process
-- import Data.VCD
import Lava.Examples.NandGate

main :: IO ()
main
= do writeSystemVerilog nandGateTop
writeSystemVerilogSimulation nandGateTop [[L, L], [H, L], [L, H], [H, H]]
callProcess "verilator" ["+1800-2017ext+sv", "verilator.vlt", "--binary", "--trace", "-Wall", "--top-module", "nandgate_sim", "nandgate.sv", "nandgate_sim.sv"]
callProcess "obj_dir/Vnandgate_sim" ["+trace"]
-- vcd_contents <- readFile "nandgate_sim.vcd"
-- putStrLn (show (parseVCD vcd_contents))
4 changes: 3 additions & 1 deletion xilinx-lava.cabal
Original file line number Diff line number Diff line change
Expand Up @@ -146,4 +146,6 @@ test-suite test-verilator
build-depends:
base >= 4.17.2 && <= 4.20.0.0,
bitvec >= 1.1.2.0,
xilinx-lava
xilinx-lava,
process,
vcd ^>=0.2.2,

0 comments on commit 14a3f93

Please sign in to comment.