remove half-baked TlsKey solution

rust-lang · Nov 10, 2023 · b8e6566 · b8e6566
1 parent 80f17ca
commit b8e6566
Show file tree

Hide file tree

Showing 3 changed files with 2 additions and 21 deletions.
diff --git a/src/shims/tls.rs b/src/shims/tls.rs
@@ -105,25 +105,12 @@ impl<'tcx> TlsData<'tcx> {
         thread_id: ThreadId,
         new_data: Scalar<Provenance>,
         cx: &impl HasDataLayout,
-        static_roots: &mut Vec<AllocId>,
     ) -> InterpResult<'tcx> {
         match self.keys.get_mut(&key) {
             Some(TlsEntry { data, .. }) => {
                 if new_data.to_target_usize(cx)? != 0 {
                     trace!("TLS key {} for thread {:?} stored: {:?}", key, thread_id, new_data);
                     data.insert(thread_id, new_data);
-                    if thread_id.to_u32() == 0 {
-                        if let Some(alloc) = (new_data.to_pointer(cx).ok())
-                            .and_then(|ptr| ptr.provenance.and_then(|prov| prov.get_alloc_id()))
-                        {
-                            trace!(
-                                "TLS key {} for main thread stored as static root: {:?}",
-                                key,
-                                alloc,
-                            );
-                            static_roots.push(alloc);
-                        }
-                    }
                 } else {
                     trace!("TLS key {} for thread {:?} removed", key, thread_id);
                     data.remove(&thread_id);

diff --git a/src/shims/unix/foreign_items.rs b/src/shims/unix/foreign_items.rs
@@ -342,7 +342,7 @@ pub trait EvalContextExt<'mir, 'tcx: 'mir>: crate::MiriInterpCxExt<'mir, 'tcx> {
                 let key = this.read_scalar(key)?.to_bits(key.layout.size)?;
                 let active_thread = this.get_active_thread();
                 let new_data = this.read_scalar(new_ptr)?;
-                this.machine.tls.store_tls(key, active_thread, new_data, &*this.tcx, &mut this.machine.static_roots)?;
+                this.machine.tls.store_tls(key, active_thread, new_data, &*this.tcx)?;
 
                 // Return success (`0`).
                 this.write_null(dest)?;

diff --git a/src/shims/windows/foreign_items.rs b/src/shims/windows/foreign_items.rs
@@ -230,13 +230,7 @@ pub trait EvalContextExt<'mir, 'tcx: 'mir>: crate::MiriInterpCxExt<'mir, 'tcx> {
                 let key = u128::from(this.read_scalar(key)?.to_u32()?);
                 let active_thread = this.get_active_thread();
                 let new_data = this.read_scalar(new_ptr)?;
-                this.machine.tls.store_tls(
-                    key,
-                    active_thread,
-                    new_data,
-                    &*this.tcx,
-                    &mut this.machine.static_roots,
-                )?;
+                this.machine.tls.store_tls(key, active_thread, new_data, &*this.tcx)?;
 
                 // Return success (`1`).
                 this.write_scalar(Scalar::from_i32(1), dest)?;