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Prepare v0.10.2 #808

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merged 5 commits into from
Jun 7, 2024
Merged

Prepare v0.10.2 #808

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13884ee
Fix set_low() and set_high() implementation for OutputPin
martinsp Jun 1, 2024
7c1b99d
Update install instructions for probe-rs
jannic May 23, 2024
0d2e81f
Fix transmutes
jannic May 24, 2024
5cb727e
Fix formatting in pin_sealed.rs
jannic May 27, 2024
ce1cc05
Prepare release 0.10.2
martinsp Jun 1, 2024
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6 changes: 4 additions & 2 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ You may also want to install these helpful tools:
# Useful to creating UF2 images for the RP2040 USB Bootloader
cargo install elf2uf2-rs --locked
# Useful for flashing over the SWD pins using a supported JTAG probe
cargo install probe-rs --features cli --locked
cargo install --locked probe-rs-tools
```

## Packages
Expand Down Expand Up @@ -196,9 +196,11 @@ probe-rs can autodetect your debug probe, which can make it easier to use.
*Step 1* - Install `probe-rs`:

```console
$ cargo install probe-rs --features cli --locked
$ cargo install --locked probe-rs-tools
```

Alternatively, follow the installation instructions on https://probe.rs/.

*Step 2* - Make sure your .cargo/config contains the following:

```toml
Expand Down
8 changes: 7 additions & 1 deletion rp2040-hal/CHANGELOG.md
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Expand Up @@ -7,7 +7,12 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

## [Unreleased]

## [0.10.2] - 2024-06-07

- Fix oneshot adc read waiting indefinitely - #799 @mjptree
- Fix set_low() and set_high() implementation for OutputPin - #807 @martinsp
- Update install instructions for probe-rs - #804 @jannic
- Fix bad transmutes of references to Qspi pins - #805 @jannic

## [0.10.1] - 2024-04-28

Expand Down Expand Up @@ -407,7 +412,8 @@ The Minimum-Supported Rust Version (MSRV) for this release is 1.54.

- Initial release

[Unreleased]: https://github.com/rp-rs/rp-hal/compare/v0.10.1...HEAD
[Unreleased]: https://github.com/rp-rs/rp-hal/compare/v0.10.2...HEAD
[0.10.2]: https://github.com/rp-rs/rp-hal/compare/v0.10.1...v0.10.2
[0.10.1]: https://github.com/rp-rs/rp-hal/compare/v0.10.0...v0.10.1
[0.10.0]: https://github.com/rp-rs/rp-hal/compare/v0.9.1...v0.10.0
[0.9.1]: https://github.com/rp-rs/rp-hal/compare/v0.9.0...v0.9.1
Expand Down
2 changes: 1 addition & 1 deletion rp2040-hal/Cargo.toml
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@@ -1,6 +1,6 @@
[package]
name = "rp2040-hal"
version = "0.10.1"
version = "0.10.2"
authors = ["The rp-rs Developers"]
edition = "2021"
homepage = "https://github.com/rp-rs/rp-hal"
Expand Down
13 changes: 9 additions & 4 deletions rp2040-hal/src/gpio/mod.rs
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Expand Up @@ -1465,8 +1465,8 @@ mod eh1 {
use embedded_hal::digital::{ErrorType, InputPin, OutputPin, StatefulOutputPin};

use super::{
func, AnyPin, AsInputPin, Error, FunctionSio, InOutPin, Pin, PinId, PullType, SioConfig,
SioInput, SioOutput,
func, AnyPin, AsInputPin, Error, FunctionSio, InOutPin, OutputEnableOverride, Pin, PinId,
PullType, SioConfig, SioInput, SioOutput,
};

impl<I, P, S> ErrorType for Pin<I, FunctionSio<S>, P>
Expand Down Expand Up @@ -1558,12 +1558,17 @@ mod eh1 {
I: AnyPin,
{
fn set_low(&mut self) -> Result<(), Self::Error> {
self.inner._set_low();
// The pin is already set to output low but this is inhibited by the override.
self.inner
.set_output_enable_override(OutputEnableOverride::Enable);
Ok(())
}

fn set_high(&mut self) -> Result<(), Self::Error> {
self.inner._set_high();
// To set the open-drain pin to high, just disable the output driver by configuring the
// output override. That way, the DHT11 can still pull the data line down to send its response.
self.inner
.set_output_enable_override(OutputEnableOverride::Disable);
Ok(())
}
}
Expand Down
64 changes: 39 additions & 25 deletions rp2040-hal/src/gpio/pin/pin_sealed.rs
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Expand Up @@ -43,8 +43,8 @@ macro_rules! accessor_fns {
unsafe {
let sio = &*$crate::pac::SIO::PTR;
match pin.bank {
DynBankId::Bank0 => &sio.[<gpio_ $reg:lower>](),
DynBankId::Qspi => core::mem::transmute(&sio.[<gpio_hi_ $reg:lower>]()),
DynBankId::Bank0 => sio.[<gpio_ $reg:lower>](),
DynBankId::Qspi => core::mem::transmute::<&$crate::pac::sio::[<GPIO_HI_ $reg:upper>],&$crate::pac::sio::[<GPIO_ $reg:upper>]>(sio.[<gpio_hi_ $reg:lower>]()),
}
}
}
Expand All @@ -57,19 +57,11 @@ macro_rules! accessor_fns {
match pin.bank {
DynBankId::Bank0 => {
let gpio = unsafe { &*$crate::pac::IO_BANK0::PTR };
&gpio.gpio(usize::from(pin.num)).[<gpio_ $reg:lower>]()
gpio.gpio(usize::from(pin.num)).[<gpio_ $reg:lower>]()
}
DynBankId::Qspi => unsafe {
let qspi = &*$crate::pac::IO_QSPI::PTR;
match pin.num {
0 => core::mem::transmute(&qspi.gpio_qspisclk().[<gpio_ $reg:lower>]()),
1 => core::mem::transmute(&qspi.gpio_qspiss().[<gpio_ $reg:lower>]()),
2 => core::mem::transmute(&qspi.gpio_qspisd0().[<gpio_ $reg:lower>]()),
3 => core::mem::transmute(&qspi.gpio_qspisd1().[<gpio_ $reg:lower>]()),
4 => core::mem::transmute(&qspi.gpio_qspisd2().[<gpio_ $reg:lower>]()),
5 => core::mem::transmute(&qspi.gpio_qspisd3().[<gpio_ $reg:lower>]()),
_ => unreachable!("Invalid QSPI bank pin number."),
}
core::mem::transmute::<&$crate::pac::io_qspi::gpio_qspi::[<GPIO_ $reg:upper>], &$crate::pac::io_bank0::gpio::[<GPIO_ $reg:upper>]>(qspi.gpio_qspi(usize::from(pin.num)).[<gpio_ $reg:lower>]())
},
}
}
Expand All @@ -86,14 +78,14 @@ macro_rules! accessor_fns {
let bank = &*$crate::pac::IO_BANK0::PTR;
match proc {
CoreId::Core0 => bank.[<proc0_ $reg:lower>](usize::from(index)),
CoreId::Core1 => core::mem::transmute(&bank.[<proc1_ $reg:lower>](usize::from(index))),
CoreId::Core1 => core::mem::transmute::<&$crate::pac::io_bank0::[<PROC1_ $reg:upper>], &$crate::pac::io_bank0::[<PROC0_ $reg:upper>]>(bank.[<proc1_ $reg:lower>](usize::from(index))),
}
}
DynBankId::Qspi => {
let bank = &*$crate::pac::IO_QSPI::PTR;
match proc {
CoreId::Core0 => core::mem::transmute(&bank.[<proc0_ $reg:lower>]()),
CoreId::Core1 => core::mem::transmute(&bank.[<proc1_ $reg:lower>]()),
CoreId::Core0 => core::mem::transmute::<&$crate::pac::io_qspi::[<PROC0_ $reg:upper>], &$crate::pac::io_bank0::[<PROC0_ $reg:upper>]>(bank.[<proc0_ $reg:lower>]()),
CoreId::Core1 => core::mem::transmute::<&$crate::pac::io_qspi::[<PROC1_ $reg:upper>], &$crate::pac::io_bank0::[<PROC0_ $reg:upper>]>(bank.[<proc1_ $reg:lower>]()),
}
}
};
Expand All @@ -115,7 +107,7 @@ macro_rules! accessor_fns {
}
DynBankId::Qspi => {
let bank = &*$crate::pac::IO_QSPI::PTR;
core::mem::transmute(&bank.[< dormant_wake_ $reg:lower>]())
core::mem::transmute::<&$crate::pac::io_qspi::[< DORMANT_WAKE_ $reg:upper >], &$crate::pac::io_bank0::[< DORMANT_WAKE_ $reg:upper >]>(bank.[< dormant_wake_ $reg:lower>]())
}
};
(reg, usize::from(offset))
Expand All @@ -140,13 +132,32 @@ where
}
DynBankId::Qspi => unsafe {
let qspi = &*pac::PADS_QSPI::PTR;
use rp2040_pac::{generic::Reg, pads_bank0, pads_qspi};
match pin.num {
0 => core::mem::transmute(&qspi.gpio_qspi_sclk()),
1 => core::mem::transmute(&qspi.gpio_qspi_ss()),
2 => core::mem::transmute(&qspi.gpio_qspi_sd0()),
3 => core::mem::transmute(&qspi.gpio_qspi_sd1()),
4 => core::mem::transmute(&qspi.gpio_qspi_sd2()),
5 => core::mem::transmute(&qspi.gpio_qspi_sd3()),
0 => core::mem::transmute::<
&Reg<pads_qspi::gpio_qspi_sclk::GPIO_QSPI_SCLK_SPEC>,
&Reg<pads_bank0::gpio::GPIO_SPEC>,
>(qspi.gpio_qspi_sclk()),
1 => core::mem::transmute::<
&Reg<pads_qspi::gpio_qspi_ss::GPIO_QSPI_SS_SPEC>,
&Reg<pads_bank0::gpio::GPIO_SPEC>,
>(qspi.gpio_qspi_ss()),
2 => core::mem::transmute::<
&Reg<pads_qspi::gpio_qspi_sd0::GPIO_QSPI_SD0_SPEC>,
&Reg<pads_bank0::gpio::GPIO_SPEC>,
>(qspi.gpio_qspi_sd0()),
3 => core::mem::transmute::<
&Reg<pads_qspi::gpio_qspi_sd1::GPIO_QSPI_SD1_SPEC>,
&Reg<pads_bank0::gpio::GPIO_SPEC>,
>(qspi.gpio_qspi_sd1()),
4 => core::mem::transmute::<
&Reg<pads_qspi::gpio_qspi_sd2::GPIO_QSPI_SD2_SPEC>,
&Reg<pads_bank0::gpio::GPIO_SPEC>,
>(qspi.gpio_qspi_sd2()),
5 => core::mem::transmute::<
&Reg<pads_qspi::gpio_qspi_sd3::GPIO_QSPI_SD3_SPEC>,
&Reg<pads_bank0::gpio::GPIO_SPEC>,
>(qspi.gpio_qspi_sd3()),
_ => unreachable!("Invalid QSPI bank pin number."),
}
},
Expand All @@ -165,13 +176,16 @@ where
accessor_fns!(sio oe_clr);
accessor_fns!(sio oe_xor);

fn proc_in_by_pass(&self) -> &crate::pac::syscfg::PROC_IN_SYNC_BYPASS {
fn proc_in_by_pass(&self) -> &pac::syscfg::PROC_IN_SYNC_BYPASS {
let pin = self.as_dyn();
unsafe {
let syscfg = &*pac::SYSCFG::PTR;
match pin.bank {
DynBankId::Bank0 => syscfg.proc_in_sync_bypass(),
DynBankId::Qspi => core::mem::transmute(&syscfg.proc_in_sync_bypass_hi()),
DynBankId::Qspi => core::mem::transmute::<
&pac::syscfg::PROC_IN_SYNC_BYPASS_HI,
&pac::syscfg::PROC_IN_SYNC_BYPASS,
>(syscfg.proc_in_sync_bypass_hi()),
}
}
}
Expand All @@ -187,7 +201,7 @@ where
}
DynBankId::Qspi => {
let bank = &*pac::IO_QSPI::PTR;
core::mem::transmute(&bank.intr())
core::mem::transmute::<&pac::io_qspi::INTR, &pac::io_bank0::INTR>(bank.intr())
}
};

Expand Down
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