mull

rizinorg · Nov 24, 2024 · 60728cb · 60728cb
1 parent 266b61b
commit 60728cb
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diff --git a/librz/arch/isa/xtensa/xtensa_il.c b/librz/arch/isa/xtensa/xtensa_il.c
@@ -772,6 +772,13 @@ static RzAnalysisLiftedILOp op_mul16u(XtensaContext *ctx) {
 		SETG(REGN(0), MUL(VARL("ars"), VARL("art"))));
 }
 
+static RzAnalysisLiftedILOp op_mull(XtensaContext *ctx) {
+	return SEQ3(
+		SETL("ars", UNSIGNED(64, IREG(1))),
+		SETL("art", UNSIGNED(64, IREG(2))),
+		SETG(REGN(0), UNSIGNED(32, MUL(VARL("ars"), VARL("art")))));
+}
+
 #include <rz_il/rz_il_opbuilder_end.h>
 
 static const fn_analyze_op_il fn_tbl[] = {
@@ -935,6 +942,7 @@ static const fn_analyze_op_il fn_tbl[] = {
 	[XTENSA_INS_MULA_DD_LH_LDINC] = op_mula_da_ldinc,
 	[XTENSA_INS_MULA_DD_HL_LDINC] = op_mula_da_ldinc,
 	[XTENSA_INS_MULA_DD_HH_LDINC] = op_mula_da_ldinc,
+	[XTENSA_INS_MULL] = op_mull,
 };
 
 void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {

diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa
@@ -175,3 +175,4 @@ d "mula.dd.ll.ldinc m0, a1, m0, m2" 040108 0x0 (seq (set m1 (& (>> (var m0) (bv
 d "mula.dd.hl.ldinc m0, a1, m0, m2" 040109 0x0 (seq (set m1 (>> (var m0) (bv 32 0x10) false)) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (+ (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr)))
 d "mula.dd.lh.ldinc m0, a1, m0, m2" 04010a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (>> (var m2) (bv 32 0x10) false)) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (+ (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr)))
 d "mula.dd.hh.ldinc m0, a1, m0, m2" 04010b 0x0 (seq (set m1 (>> (var m0) (bv 32 0x10) false)) (set m2 (>> (var m2) (bv 32 0x10) false)) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (+ (var a1) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a1 (var vAddr)))
+d "mull a2, a3, a1" 102382 0x0 (seq (set ars (cast 64 false (var a3))) (set art (cast 64 false (var a1))) (set a2 (cast 32 false (* (var ars) (var art)))))