Merge branch 'qemu-for-testing' into riscv-all

Makefile.objs

@@ -228,6 +228,7 @@ trace-events-subdirs += hw/nvram
 trace-events-subdirs += hw/pci
 trace-events-subdirs += hw/pci-host
 trace-events-subdirs += hw/ppc
+trace-events-subdirs += hw/riscv
 trace-events-subdirs += hw/rdma
 trace-events-subdirs += hw/rdma/vmw
 trace-events-subdirs += hw/s390x

configure

@@ -7044,12 +7044,14 @@ case "$target_name" in
     TARGET_BASE_ARCH=riscv
     TARGET_ABI_DIR=riscv
     mttcg=yes
+    gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml"
     target_compiler=$cross_cc_riscv32
   ;;
   riscv64)
     TARGET_BASE_ARCH=riscv
     TARGET_ABI_DIR=riscv
     mttcg=yes
+    gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml"
     target_compiler=$cross_cc_riscv64
   ;;
   sh4|sh4eb)

gdb-xml/riscv-cpu.xml

@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+  <reg name="x0" bitsize="64"/>
+  <reg name="x1" bitsize="64"/>
+  <reg name="x2" bitsize="64"/>
+  <reg name="x3" bitsize="64"/>
+  <reg name="x4" bitsize="64"/>
+  <reg name="x5" bitsize="64"/>
+  <reg name="x6" bitsize="64"/>
+  <reg name="x7" bitsize="64"/>
+  <reg name="x8" bitsize="64"/>
+  <reg name="x9" bitsize="64"/>
+  <reg name="x10" bitsize="64"/>
+  <reg name="x11" bitsize="64"/>
+  <reg name="x12" bitsize="64"/>
+  <reg name="x13" bitsize="64"/>
+  <reg name="x14" bitsize="64"/>
+  <reg name="x15" bitsize="64"/>
+  <reg name="x16" bitsize="64"/>
+  <reg name="x17" bitsize="64"/>
+  <reg name="x18" bitsize="64"/>
+  <reg name="x19" bitsize="64"/>
+  <reg name="x20" bitsize="64"/>
+  <reg name="x21" bitsize="64"/>
+  <reg name="x22" bitsize="64"/>
+  <reg name="x23" bitsize="64"/>
+  <reg name="x24" bitsize="64"/>
+  <reg name="x25" bitsize="64"/>
+  <reg name="x26" bitsize="64"/>
+  <reg name="x27" bitsize="64"/>
+  <reg name="x28" bitsize="64"/>
+  <reg name="x29" bitsize="64"/>
+  <reg name="x30" bitsize="64"/>
+  <reg name="x31" bitsize="64"/>
+  <reg name="pc" bitsize="64"/>
+</feature>

gdb-xml/riscv-csr.xml

@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.csr">
+  <reg name="misa" bitsize="64" regnum="0x342"/>
+</feature>

gdb-xml/riscv-fpu.xml

@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.fpu">
+  <reg name="f0" bitsize="64"/>
+  <reg name="f1" bitsize="64"/>
+  <reg name="f2" bitsize="64"/>
+  <reg name="f3" bitsize="64"/>
+  <reg name="f4" bitsize="64"/>
+  <reg name="f5" bitsize="64"/>
+  <reg name="f6" bitsize="64"/>
+  <reg name="f7" bitsize="64"/>
+  <reg name="f8" bitsize="64"/>
+  <reg name="f9" bitsize="64"/>
+  <reg name="f10" bitsize="64"/>
+  <reg name="f11" bitsize="64"/>
+  <reg name="f12" bitsize="64"/>
+  <reg name="f13" bitsize="64"/>
+  <reg name="f14" bitsize="64"/>
+  <reg name="f15" bitsize="64"/>
+  <reg name="f16" bitsize="64"/>
+  <reg name="f17" bitsize="64"/>
+  <reg name="f18" bitsize="64"/>
+  <reg name="f19" bitsize="64"/>
+  <reg name="f20" bitsize="64"/>
+  <reg name="f21" bitsize="64"/>
+  <reg name="f22" bitsize="64"/>
+  <reg name="f23" bitsize="64"/>
+  <reg name="f24" bitsize="64"/>
+  <reg name="f25" bitsize="64"/>
+  <reg name="f26" bitsize="64"/>
+  <reg name="f27" bitsize="64"/>
+  <reg name="f28" bitsize="64"/>
+  <reg name="f29" bitsize="64"/>
+  <reg name="f30" bitsize="64"/>
+  <reg name="f31" bitsize="64"/>
+  <reg name="f32" bitsize="64"/>
+</feature>

hw/riscv/Makefile.objs

@@ -2,6 +2,7 @@ obj-y += boot.o
 obj-y += riscv_htif.o
 obj-y += riscv_hart.o
 obj-y += sifive_e.o
+obj-y += sifive_clic.o
 obj-y += sifive_clint.o
 obj-y += sifive_prci.o
 obj-y += sifive_plic.o