fixing a few typos + clarification

riscv · Jan 18, 2024 · ed8f89e · ed8f89e
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Showing 3 changed files with 10 additions and 10 deletions.
diff --git a/doc/vector-extra/insns/vclmul-32e.adoc b/doc/vector-extra/insns/vclmul-32e.adoc
@@ -49,9 +49,9 @@ Arguments::
 |Direction
 |Definition
 
-| Vs1/Rs1 | input  |  multiplier
-| Vs2 | input  |  multiplicand
-| Vd  | output | carry-less product low
+| `vs1`/`rs1` | input  | multiplier
+| `vs2`       | input  | multiplicand
+| `vd`        | output | lower part of carry-less 
 |===
 
 [NOTE]
@@ -60,7 +60,7 @@ Arguments::
 ====
 
 Description::
-Produces the low half of 128-bit carry-less product.
+Produces the low half of `2*SEW`-bit carry-less product.
 
 Each SEW-bit element in the `vs2` vector register is carry-less multiplied by
 either each SEW-bit element in `vs1` (vector-vector), or the SEW-bit value

diff --git a/doc/vector-extra/insns/vclmulh-32e.adoc b/doc/vector-extra/insns/vclmulh-32e.adoc
@@ -49,9 +49,9 @@ Arguments::
 |Direction
 |Definition
 
-| Vs1 | input  | multiplier
-| Vs2 | input  | multiplicand
-| Vd  | output | carry-less product high
+| `vs1`/`rs1` | input  | multiplier
+| `vs2`       | input  | multiplicand
+| `vd`        | output | upper part of carry-less 
 |===
 
 [NOTE]
@@ -60,7 +60,7 @@ Arguments::
 ====
 
 Description::
-Produces the high half of 128-bit carry-less product.
+Produces the high half of `2*SEW`-bit carry-less product.
 
 Each SEW-bit element in the `vs2` vector register is carry-less multiplied by
 either each SEW-bit element in `vs1` (vector-vector), or the SEW-bit value

diff --git a/doc/vector-extra/riscv-crypto-vector-extra-zvbc32e.adoc b/doc/vector-extra/riscv-crypto-vector-extra-zvbc32e.adoc
@@ -1,4 +1,4 @@
-[[zvbc,Zvbc]]
+[[zvbc32e,Zvbc32e]]
 === `Zvbc32e` - Vector Carryless Multiplication
 
 General purpose carryless multiplication instructions which are commonly used in cryptography
@@ -8,7 +8,7 @@ These instructions are only defined for `SEW`=32.
 Zvbc32e can be supported when `ELEN >=32`.
 
 
-Note:: The extension `Zvbc32e` is independent from `Zvbc` where the same instructions are defined for `SEW=64`.
+Note:: The extension `Zvbc32e` is independent from `Zvbc` which defines the same instructions for `SEW=64`.
        When `ELEN>=64` both extensions can be combined to have `vclmul.v[vx]` and `vclmulh.v[vx]` defined for both `SEW=32` and `SEW=64`.
 
 [%autowidth]