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Issue Queue Implementation #140

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merged 20 commits into from
Feb 7, 2024
Merged

Issue Queue Implementation #140

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b4f58e8
Pushing current issue queue changes
aarongchan Jan 11, 2024
ed04b56
Clang formatted, flushing merged, testing fixed, issue queue implemen…
aarongchan Jan 19, 2024
dbf2403
Removing unnecessary comments, cleaning up code, addressing scoreboar…
aarongchan Jan 19, 2024
55ee5c9
Removing commented code
aarongchan Jan 19, 2024
178df25
Removing ExecutePipe.cpp import, moving determineRegstierFile to core…
aarongchan Jan 20, 2024
319a5bc
Fix for issuequeue failure
aarongchan Jan 20, 2024
6b0e363
Addressing comments
aarongchan Jan 23, 2024
fac0938
More changes addressing comments
aarongchan Jan 23, 2024
a63aff3
Pointing github action to new sparta
aarongchan Jan 23, 2024
d3027a1
Adding class for IssueQueueTester
aarongchan Jan 23, 2024
fe146ae
Addressing comments
aarongchan Jan 24, 2024
b1d0b1f
Merge branch 'master' into issue-queue
aarongchan Jan 31, 2024
067dff4
Redesign to more generic execution units
aarongchan Feb 1, 2024
3b24a5b
Removing dispatch unit from json and removing all associated code thr…
aarongchan Feb 1, 2024
fc2d18e
Removing bad test that was indexing at an out of range vlaue in refer…
aarongchan Feb 2, 2024
7bafc0a
Merge branch 'master' into issue-queue
aarongchan Feb 4, 2024
19ed4b7
Addressing comments, removing possible seg fault
aarongchan Feb 4, 2024
78e5ba0
Renaming scheme for issue queue and execution units, documentation as…
aarongchan Feb 5, 2024
55108d2
Accidentally added another .yaml file, messes up test because we rena…
aarongchan Feb 5, 2024
d6bb2fa
Debug content dump for issue queue and const & for getExepipes()
aarongchan Feb 6, 2024
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2 changes: 1 addition & 1 deletion .github/workflows/ubuntu-build.yml
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Expand Up @@ -38,7 +38,7 @@ jobs:
with:
repository: sparcians/map
path: map
ref: map_v2.0.10
ref: map_v2.0.13

# Setup Conda and build environment
- name: Grab Python v3.8
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85 changes: 58 additions & 27 deletions arches/big_core.yaml
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Expand Up @@ -18,41 +18,72 @@ top.cpu.core0:

top.cpu.core0.extension.core_extensions:
execution_topology:
[["alu", "6"],
["fpu", "2"],
["br", "2"]]
[["alu", "6"],
["fpu", "2"],
["br", "2"]]
# this defines what pipe types are assigned to which execution unit
pipe_topology_alu_pipes:
[["int"], # alu0
["int", "div"], # alu1
["int", "mul"],
["int", "mul", "i2f", "cmov"],
["int"],
["int"]]
pipe_topology_br_pipes:
[["br"],
["br"]]
pipe_topology_fpu_pipes:
[["float", "faddsub", "fmac"],
["float", "f2i"]]
# this defines which execution units are mapped to which issue queue
issue_queue_topology:
[["alu0"],
["alu1", "alu2"],
["alu3", "alu4", "alu5"],
["fpu0", "fpu1"],
["br0", "br1"]]

top.cpu.core0.rename.scoreboards:
# From
# |
# V
integer.params.latency_matrix: |
[["", "alu0", "alu1", "alu2", "alu3", "alu4", "alu5", "fpu0", "fpu1", "br0", "br1", "lsu"],
["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu5", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]]
[["", "alu0", "alu1", "alu2", "alu3", "alu4", "alu5", "fpu0", "fpu1", "br0", "br1", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu5", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]]


float.params.latency_matrix: |
[["", "alu0", "alu1", "alu2", "alu3", "alu4", "alu5", "fpu0", "fpu1", "br0", "br1", "lsu"],
["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu5", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]]
[["", "alu0", "alu1", "alu2", "alu3", "alu4", "alu5", "fpu0", "fpu1", "br0", "br1", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu5", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]]


54 changes: 38 additions & 16 deletions arches/medium_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -19,29 +19,51 @@ top.cpu.core0.extension.core_extensions:
[["alu", "3"],
["fpu", "2"],
["br", "1"]]
pipe_topology_alu_pipes:
[["int", "mul", "i2f", "cmov"],
["int", "div"],
["int"]]
pipe_topology_br_pipes:
[["br"]]
pipe_topology_fpu_pipes:
[["float", "faddsub", "fmac"], ["float", "f2i"]]
# 6 alu issue queues
issue_queue_topology:
[["alu0", "alu1"],
["alu2"],
["fpu0", "fpu1"],
["br0"]]

top.cpu.core0.rename.scoreboards:
# From
# |
# V
integer.params.latency_matrix: |
[["", "alu0", "alu1", "alu2", "fpu0", "fpu1", "br0", "lsu"],
["alu0", "1", "1", "1", "1", "1", "1", "1"],
["alu1", "1", "1", "1", "1", "1", "1", "1"],
["alu2", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1"],
["fpu1", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1"]]
[["", "alu0", "alu1", "alu2", "fpu0", "fpu1", "br0", "lsu", "iq0", "iq1", "iq2", "iq3"],
["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]]


float.params.latency_matrix: |
[["", "alu0", "alu1", "alu2", "fpu0", "fpu1", "br0", "lsu"],
["alu0", "1", "1", "1", "1", "1", "1", "1"],
["alu1", "1", "1", "1", "1", "1", "1", "1"],
["alu2", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1"],
["fpu1", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1"]]
[["", "alu0", "alu1", "alu2", "fpu0", "fpu1", "br0", "lsu", "iq0", "iq1", "iq2", "iq3"],
["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"],
["iq3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]]

37 changes: 27 additions & 10 deletions arches/small_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -16,21 +16,38 @@ top.cpu.core0.extension.core_extensions:
[["alu", "1"],
["fpu", "1"],
["br", "1"]]
pipe_topology_alu_pipes:
[["int", "mul", "i2f", "cmov", "div"]]
pipe_topology_br_pipes:
[["br"]]
pipe_topology_fpu_pipes:
[["float", "faddsub", "fmac", "f2i"]]
# 6 alu issue queues
issue_queue_topology:
[["alu0"],
["fpu0"],
["br0"]]

top.cpu.core0.rename.scoreboards:
# From
# |
# V
integer.params.latency_matrix: |
[["", "alu0", "fpu0", "br0", "lsu"], # <-- TO
["alu0", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1"]]
[["", "alu0", "fpu0", "br0", "lsu", "iq0", "iq1", "iq2"], # <-- TO
["alu0", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1"],
["iq0", "1", "1", "1", "1", "1", "1", "1"],
["iq1", "1", "1", "1", "1", "1", "1", "1"],
["iq2", "1", "1", "1", "1", "1", "1", "1"]]

float.params.latency_matrix: |
[["", "alu0", "fpu0", "br0", "lsu"], # <-- TO
["alu0", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1"]]
[["", "alu0", "fpu0", "br0", "lsu", "iq0", "iq1", "iq2"], # <-- TO
["alu0", "1", "1", "1", "1", "1", "1", "1"],
["fpu0", "1", "1", "1", "1", "1", "1", "1"],
["br0", "1", "1", "1", "1", "1", "1", "1"],
["lsu", "1", "1", "1", "1", "1", "1", "1"],
["iq0", "1", "1", "1", "1", "1", "1", "1"],
["iq1", "1", "1", "1", "1", "1", "1", "1"],
["iq2", "1", "1", "1", "1", "1", "1", "1"]]
1 change: 1 addition & 0 deletions core/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ add_library(core
InstArchInfo.cpp
InstGroup.cpp
InstGenerator.cpp
IssueQueue.cpp
ROB.cpp
LSU.cpp
MMU.cpp
Expand Down
37 changes: 21 additions & 16 deletions core/CPUFactories.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@
#include "FlushManager.hpp"
#include "Preloader.hpp"
#include "MavisUnit.hpp"
#include "IssueQueue.hpp"

namespace olympia{

Expand All @@ -34,69 +35,73 @@ namespace olympia{
*/
struct CPUFactories{

//! \brief Resouce Factory to build a Core Unit
//! \brief Resource Factory to build a Core Unit
sparta::ResourceFactory<olympia::Core,
olympia::Core::CoreParameterSet> core_rf;

//! \brief Resouce Factory to build a Fetch Unit
//! \brief Resource Factory to build a Fetch Unit
sparta::ResourceFactory<olympia::Fetch,
olympia::Fetch::FetchParameterSet> fetch_rf;

//! \brief Resouce Factory to build a Decode Unit
//! \brief Resource Factory to build a Decode Unit
sparta::ResourceFactory<olympia::Decode,
olympia::Decode::DecodeParameterSet> decode_rf;

//! \brief Resouce Factory to build a Rename Unit
//! \brief Resource Factory to build a Rename Unit
RenameFactory rename_rf;

//! \brief Resouce Factory to build a Dispatch Unit
//! \brief Resource Factory to build a Dispatch Unit
DispatchFactory dispatch_rf;

//! \brief Resouce Factory to build a Execute Unit
//! \brief Resource Factory to build a Execute Unit
ExecuteFactory execute_rf;


//! \brief Resouce Factory to build a MMU Unit
//! \brief Resource Factory to build a MMU Unit
sparta::ResourceFactory<olympia::DCache,
olympia::DCache::CacheParameterSet> dcache_rf;

//! \brief Resouce Factory to build a TLB Unit
//! \brief Resource Factory to build a TLB Unit
sparta::ResourceFactory<olympia::SimpleTLB,
olympia::SimpleTLB::TLBParameterSet> tlb_rf;

//! \brief Resouce Factory to build a MMU Unit
//! \brief Resource Factory to build a MMU Unit
sparta::ResourceFactory<olympia::MMU,
olympia::MMU::MMUParameterSet> mmu_rf;

//! \brief Resouce Factory to build a LSU Unit
//! \brief Resource Factory to build a LSU Unit
sparta::ResourceFactory<olympia::LSU,
olympia::LSU::LSUParameterSet> lsu_rf;

//! \brief Resouce Factory to build a L2Cache Unit
sparta::ResourceFactory<olympia_mss::L2Cache,
olympia_mss::L2Cache::L2CacheParameterSet> l2cache_rf;

//! \brief Resouce Factory to build a BIU Unit
//! \brief Resource Factory to build a BIU Unit
sparta::ResourceFactory<olympia_mss::BIU,
olympia_mss::BIU::BIUParameterSet> biu_rf;

//! \brief Resouce Factory to build a MSS Unit
//! \brief Resource Factory to build a MSS Unit
sparta::ResourceFactory<olympia_mss::MSS,
olympia_mss::MSS::MSSParameterSet> mss_rf;

//! \brief Resouce Factory to build a ROB Unit
//! \brief Resource Factory to build a ROB Unit
sparta::ResourceFactory<olympia::ROB,
olympia::ROB::ROBParameterSet> rob_rf;

//! \brief Resouce Factory to build a Flush Unit
//! \brief Resource Factory to build a Flush Unit
sparta::ResourceFactory<olympia::FlushManager,
olympia::FlushManager::FlushManagerParameters> flushmanager_rf;

//! \brief Resouce Factory to build a Preloader Unit
//! \brief Resource Factory to build a Preloader Unit
sparta::ResourceFactory<olympia::Preloader,
olympia::Preloader::PreloaderParameterSet> preloader_rf;

// //! \brief Resource Factory to build a IssueQueue Unit
// sparta::ResourceFactory<olympia::IssueQueue,
// olympia::IssueQueue::IssueQueueParameterSet> issue_queue_rf;

//! \brief Set up the Mavis Decode functional unit
MavisFactoy mavis_rf;
MavisFactory mavis_rf;
}; // struct CPUFactories
} // namespace olympia
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