vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vecto…

…r widening floating-point fused multiply-add instructions
riscv-software-src · Sep 3, 2024 · 6a1a5db · 6a1a5db
1 parent b47d0ba
commit 6a1a5db
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/disasm/disasm.cc b/disasm/disasm.cc
@@ -1970,10 +1970,10 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
     DISASM_OPIV_WF_INSN(vfwadd);
     DISASM_OPIV_WF_INSN(vfwsub);
     DISASM_OPIV_VF_INSN(vfwmul);
-    DISASM_OPIV_VF_INSN(vfwmacc);
-    DISASM_OPIV_VF_INSN(vfwnmacc);
-    DISASM_OPIV_VF_INSN(vfwmsac);
-    DISASM_OPIV_VF_INSN(vfwnmsac);
+    DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwmacc);
+    DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwnmacc);
+    DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwmsac);
+    DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwnmsac);
 
     #undef DISASM_OPIV_VF_INSN
     #undef DISASM_OPIV__F_INSN