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PMU fixes and fwft pr #181

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PMU fixes and fwft pr #181

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e834ad3
Add Samuel Holland to contributor list
SiFiveHolland Oct 17, 2024
8356b81
Fixes few typos in pmu spec
atishp04 Oct 17, 2024
b3aa9fa
Modify the PMU raw event v2 width to 56 bits
atishp04 Oct 17, 2024
4542d28
Fix the typo with the the raw event width
atishp04 Oct 17, 2024
a676827
ext-fwft: use uint32_t type for `feature` parameters
clementleger Oct 17, 2024
05a602c
Merge branch 'riscv-non-isa:master' into pmu_fixes_pr
atishp04 Oct 29, 2024
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4 changes: 2 additions & 2 deletions src/ext-firmware-features.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ description. Upon system reset, global and local feature values are reset.

[source, C]
----
struct sbiret sbi_fwft_set(unsigned long feature,
struct sbiret sbi_fwft_set(uint32_t feature,
unsigned long value,
unsigned long flags)
----
Expand Down Expand Up @@ -161,7 +161,7 @@ switch if delegation choices are different between Host and Guest/VM.

[source, C]
----
struct sbiret sbi_fwft_get(unsigned long feature)
struct sbiret sbi_fwft_get(uint32_t feature)
----

A successful return from `sbi_fwft_get()` results in the firmware
Expand Down
12 changes: 6 additions & 6 deletions src/ext-pmu.adoc
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Expand Up @@ -52,9 +52,9 @@ specification.
| Type #0 | 0 | Hardware general events
| Type #1 | 1 | Hardware Cache events
| Type #2 | 2 | Hardware raw events (deprecated)
Bits allowed for mhpmeventX [0:48]
Bits allowed for mhpmeventX [0:47]
| Type #3 | 3 | Hardware raw events v2
Bits allowed for mhpmeventX [0:58]
Bits allowed for mhpmeventX [0:55]
| Type #15 | 15 | Firmware events
|===

Expand Down Expand Up @@ -189,8 +189,8 @@ configuration (or parameter) should have the 32-bit value to to be programmed
in the `mhpmeventX` CSR.

On RISC-V platforms with 64 bits wide `mhpmeventX` CSRs, the `event_data`
configuration (or parameter) should have the 58-bit value be programmed
in the lower 58-bits of `mhpmeventX` CSR and the SBI implementation shall
configuration (or parameter) should have the 56-bit value be programmed
in the lower 56-bits of `mhpmeventX` CSR and the SBI implementation shall
determine the value to be programmed in the upper 6 bits of `mhpmeventX`
CSR based on privilege specification definition.

Expand Down Expand Up @@ -592,7 +592,7 @@ implement it.
Any future revisions to this structure should be made in a backward compatible
manner and will be associated with an SBI version.

The logical counter indicies in the `counter_overflow_bitmap` and `counter_values`
The logical counter indices in the `counter_overflow_bitmap` and `counter_values`
array are relative w.r.t to `counter_idx_base` argument present in the
`sbi_pmu_counter_stop` and `sbi_pmu_counter_start` functions. This allows the
users to use snapshot feature for more than XLEN counters if required.
Expand Down Expand Up @@ -650,7 +650,7 @@ must be encoded as follows:
BIT[20:31] - Reserved for the future purpose.
Must be zero.
| 1 | output | RW | BIT[0] - Boolean value to indicate `event_idx`
is supported or not. The SBI implmenentation
is supported or not. The SBI implementation
MUST update this entire 32-bit word if valid
`event_idx` and `event_data` (if applicable) are
specified in the entry. BIT[1:31] - Reserved for
Expand Down
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