Releases: riscv-non-isa/riscv-arch-test
Releases · riscv-non-isa/riscv-arch-test
3.8.2.3
-Fixed typo in regex in 3.8.2.2
3.8.2.2
- Restored *RV32 Check ISA attributes to RV32IM test cases where they were dropped in 3.8.2. Missed these on 3.8.2.1.
3.8.2.1
- Restored *RV64 Check ISA attributes to RV64IM test
cases where they were dropped in 3.8.2. Similar to 3.7.5
3.8.2
- Added "most negative number divided by -1" case for RV64IM and RV32IM in remw, divw, div and rem tests
3.8.1
- Updated trap handler to avoid using mstatush when used for Priv Arch 1.11
- Updated GOTO_Lower_Mode macro to adjust the save area when switching to Umode.
3.8.0
- Updated trap handler to handle delegated exceptions in S-mode for both bare and virtual modes.
- Added Hypervisor mode support in Trap handler
- Updated the save area within the trap handler file.
- Improved CSR Rename macro for code clarity.
3.7.5
Add missing check ISA fields in recently modified div and amo tests
3.7.4
- Fix typos in CONTRIBUTION.md
3.7.3
- Added test RV32i_m/div-01.S and RV64i_m/div-01.S tests.
- Added tests for resolving missing coverage issue of harcoded registersissue #306
3.7.2
- Modified macros to allow assembling tests with LLVM 18+