Added *RV64 to checkISA for RV64 M tests that lost this attribute.

riscv-non-isa · Nov 15, 2023 · 4e61c25 · 4e61c25
1 parent 4eea0a0
commit 4e61c25
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Showing 7 changed files with 7 additions and 7 deletions.
diff --git a/riscv-test-suite/rv64i_m/M/src/divu-01.S b/riscv-test-suite/rv64i_m/M/src/divu-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",divu)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",divu)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/M/src/mul-01.S b/riscv-test-suite/rv64i_m/M/src/mul-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mul)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",mul)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/M/src/mulh-01.S b/riscv-test-suite/rv64i_m/M/src/mulh-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulh)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",mulh)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S b/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulhsu)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",mulhsu)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/M/src/mulhu-01.S b/riscv-test-suite/rv64i_m/M/src/mulhu-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulhu)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",mulhu)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/M/src/rem-01.S b/riscv-test-suite/rv64i_m/M/src/rem-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",rem)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",rem)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv64i_m/M/src/remu-01.S b/riscv-test-suite/rv64i_m/M/src/remu-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",remu)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",remu)
 
 RVTEST_SIGBASE(x1,signature_x1_1)