Merge pull request #370 from ved-rivos/zacas

Add ratified Zacas extension

CHANGELOG.md

@@ -1,4 +1,6 @@
 # CHANGELOG
+## [3.8.18] - 2023-07-28
+- Add Zacas ISA extension support.
 
 ## [3.8.17] - 2024-05-03
 - Add Zfa support.
@@ -117,6 +119,7 @@ Add missing check ISA fields in recently modified div and amo tests
 - Added test case for division if most negative number by -1
 - Solved the [issue #300](https://github.com/riscv-non-isa/riscv-arch-test/issues/300)
 
+
 ## [3.7.0] - 2023-05-16
 - Updated the LI macro
 - Make Trap handler compatible for RV32E

coverage/dataset.cgf

@@ -144,6 +144,23 @@ datasets:
     x30: 0
     x31: 0
 
+  pair_regs: &pair_regs
+    x2: 0
+    x4: 0
+    x6: 0
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+    x16: 0
+    x18: 0
+    x20: 0
+    x22: 0
+    x24: 0
+    x26: 0
+    x28: 0
+    x30: 0
+
   cbfmt_immval_sgn: &cbfmt_immval_sgn
     'imm_val == (-2**(6-1))': 0
     'imm_val == 0': 0
@@ -321,3 +338,93 @@ datasets:
     'walking_zeros("imm_val", 12,False)': 0
     'alternate("imm_val",12,False)': 0
 
+  rvp64_rs1val_sgn: &rvp64_rs1val_sgn
+    'rs1_val == (-2**63)': 0
+    'rs1_val == 0': 0
+    'rs1_val == (2**63-1)': 0
+    'rs1_val == 1': 0
+
+  rvp64_rs2val_sgn: &rvp64_rs2val_sgn
+    'rs2_val == (-2**63)': 0
+    'rs2_val == 0': 0
+    'rs2_val == (2**63-1)': 0
+    'rs2_val == 1': 0
+
+  rvp64_rs1val_unsgn: &rvp64_rs1val_unsgn
+    'rs1_val == 0': 0
+    'rs1_val == (2**64-1)': 0
+    'rs1_val == 1': 0
+
+  rvp64_rs2val_unsgn: &rvp64_rs2val_unsgn
+    'rs2_val == 0': 0
+    'rs2_val == (2**64-1)': 0
+    'rs2_val == 1': 0
+
+  rvp64_rs1val_walking_sgn: &rvp64_rs1val_walking_sgn
+    'walking_ones("rs1_val", 64)': 0
+    'walking_zeros("rs1_val", 64)': 0
+    'alternate("rs1_val",64)': 0
+
+  rvp64_rs2val_walking_sgn: &rvp64_rs2val_walking_sgn
+    'walking_ones("rs2_val", 64)': 0
+    'walking_zeros("rs2_val", 64)': 0
+    'alternate("rs2_val",64)': 0
+
+  rvp64_rs1val_walking_unsgn: &rvp64_rs1val_walking_unsgn
+    'walking_ones("rs1_val", 64, signed=False)': 0
+    'walking_zeros("rs1_val", 64, signed=False)': 0
+    'alternate("rs1_val",64, signed=False)': 0
+
+  rvp64_rs2val_walking_unsgn: &rvp64_rs2val_walking_unsgn
+    'walking_ones("rs2_val", 64, signed=False)': 0
+    'walking_zeros("rs2_val", 64, signed=False)': 0
+    'alternate("rs2_val",64, signed=False)': 0
+
+  rvp128_rs1val_sgn: &rvp128_rs1val_sgn
+    'rs1_val == 0': 0
+    'rs1_val == 1': 0
+
+  rvp128_rs2val_sgn: &rvp128_rs2val_sgn
+    'rs2_val == 0': 0
+    'rs2_val == 1': 0
+
+  rvp128_rs1val_walking_sgn: &rvp128_rs1val_walking_sgn
+    'walking_ones("rs1_val", 128)': 0
+    'walking_zeros("rs1_val", 128)': 0
+    'alternate("rs1_val",128)': 0
+
+  rvp128_rs2val_walking_sgn: &rvp128_rs2val_walking_sgn
+    'walking_ones("rs2_val", 128)': 0
+    'walking_zeros("rs2_val", 128)': 0
+    'alternate("rs2_val",128)': 0
+
+  zacas_op_comb: &zacas_op_comb
+    'rs1 != rs2  and rs1 != rd and rs2 != rd': 0
+
+  zacas_dcas_rs1val_sgn: &zacas_dcas_rs1val_sgn
+    'rs1_val == 0': 0
+    'rs1_val == 1': 0
+
+  zacas_dcas_rs2val_sgn: &zacas_dcas_rs2val_sgn
+    'rs2_val == 0': 0
+    'rs2_val == 1': 0
+
+  zacas128_rs1val_walking_sgn: &zacas128_rs1val_walking_sgn
+    'walking_ones("rs1_val", 128)': 0
+    'walking_zeros("rs1_val", 128)': 0
+    'alternate("rs1_val",128)': 0
+
+  zacas128_rs2val_walking_sgn: &zacas128_rs2val_walking_sgn
+    'walking_ones("rs2_val", 128)': 0
+    'walking_zeros("rs2_val", 128)': 0
+    'alternate("rs2_val",128)': 0
+
+  zacas64_rs1val_walking_sgn: &zacas64_rs1val_walking_sgn
+    'walking_ones("rs1_val", 64)': 0
+    'walking_zeros("rs1_val", 64)': 0
+    'alternate("rs1_val",64)': 0
+
+  zacas64_rs2val_walking_sgn: &zacas64_rs2val_walking_sgn
+    'walking_ones("rs2_val", 64)': 0
+    'walking_zeros("rs2_val", 64)': 0
+    'alternate("rs2_val",64)': 0

coverage/rv32zacas.cgf

@@ -0,0 +1,36 @@
+# cover group format file for Zacas extension
+amocas.w:
+    config: 
+      - check ISA:=regex(.*Zacas.*)
+    opcode: 
+      amocas.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn, *base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking, *rs2val_walking]
+
+amocas.d_32:
+    config:
+      - check ISA:=regex(.*Zacas.*)
+    opcode:
+      amocas.d_32: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *pair_regs
+    rd:
+      <<: *pair_regs
+    op_comb:
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn]
+      abstract_comb:
+        <<: [*zacas64_rs1val_walking_sgn, *zacas64_rs2val_walking_sgn]

coverage/rv64zacas.cgf

@@ -0,0 +1,54 @@
+# cover group format file for Zacas extension
+amocas.w:
+    config: 
+      - check ISA:=regex(.*Zacas.*)
+    opcode: 
+      amocas.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn, *base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking, *rs2val_walking]
+
+amocas.d_64:
+    config: 
+      - check ISA:=regex(.*Zacas.*)
+    opcode: 
+      amocas.d_64: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn, *base_rs2val_sgn, *rfmt_val_comb_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking, *rs2val_walking]
+
+amocas.q:
+    config:
+      - check ISA:=regex(.*Zacas.*)
+    opcode:
+      amocas.q: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *pair_regs
+    rd:
+      <<: *pair_regs
+    op_comb:
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn]
+      abstract_comb:
+        <<: [*zacas128_rs1val_walking_sgn, *zacas128_rs2val_walking_sgn]

riscv-test-suite/env/test_macros.h

@@ -1099,6 +1099,56 @@ ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
     sub x1,x1,tempreg			;\
     RVTEST_SIGUPD(swreg,x1,offset) 
 
+// for updating signatures of Zacas paired destination register (RV32/RV64).
+#define RVTEST_SIGUPD_PZACAS(_BR,_R1,_R2,...)		;\
+  .if NARG(__VA_ARGS__) == 1				;\
+      .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
+  .endif						;\
+  .if (offset & (REGWIDTH-1)) != 0			;\
+      .warning "Signature Incorrect Offset Alignment."	;\
+     .set offset, offset&(SIGALIGN-1)+SIGALIGN		;\
+  .endif						;\
+      CHK_OFFSET(_BR,REGWIDTH,0)			;\
+      SREG _R1,offset(_BR)				;\
+      CHK_OFFSET(_BR,REGWIDTH,1)			;\
+      SREG _R2,offset(_BR)				;\
+      .set offset,offset+(REGWIDTH)
+
+// Tests for a AMOCAS where operation width is <= xlen
+// First store a value that will cause a mismatch on cas
+// Test a failing amocas followed by a successful amocas
+#define TEST_CAS_OP(inst, rd, rs1, rs2, swap_val, sigptr, offset) \
+    LI(rd, swap_val);\
+    neg rd, rd;\
+    LA(rs1, rvtest_data);\
+    SREG rd, (rs1);\
+    LI(rd, swap_val);\
+    LI(rs2, swap_val);\
+    LA(rs1, rvtest_data);\
+    inst rd, rs2, (rs1);\
+    inst rd, rs2, (rs1);\
+    RVTEST_SIGUPD(sigptr,rd,offset);
+
+// Tests for a AMOCAS where operation width is <= xlen
+// First store a value that will cause a mismatch on cas
+// Test a failing amocas followed by a successful amocas
+#define TEST_DCAS_OP(inst, rd, rd_hi, rs1, rs2, rs2_hi, swap_val, swap_val_hi, sigptr, offset) \
+    LA(rs1, rvtest_data);\
+    LI(rd, swap_val);\
+    neg rd, rd;\
+    SREG rd, (rs1);\
+    LI(rd, swap_val_hi);\
+    neg rd, rd;\
+    SREG rd, (__riscv_xlen/8)(rs1);\
+    LI(rd, swap_val);\
+    LI(rd_hi, swap_val_hi);\
+    LI(rs2, swap_val);\
+    LI(rs2_hi, swap_val_hi);\
+    LA(rs1, rvtest_data);\
+    inst rd, rs2, (rs1);\
+    LA(rs1, rvtest_data);\
+    inst rd, rs2, (rs1);\
+    RVTEST_SIGUPD_PZACAS(sigptr,rd,rd_hi,offset);
 
 //--------------------------------- Migration aliases ------------------------------------------
 #ifdef RV_COMPLIANCE_RV32M