[C-Ext] Fix patchable jal
s spanning cache lines
#24
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Hi team,
This patch includes several fixes for the C extension support. It contains three small patches to fix different problems or potential issues.
MacroAssembler::far_call()
has a reserved place needing a fix. Though hardly reachable, for its correctness we also need to fix it.emit_int64((intptr_t)dest)
8-byte aligned, some code needs a revise to adjust the new change. We have checked places where unalignment-related issues could occur and found this one, and now the 64-bit addresses in trampolines are properly aligned.Please see a hs_err file attached.
In short, patchable instructions' patching bits must not span cache lines. Concisely, the problem is that, after the C extension instructions get 2-byte aligned. Patchable
jal
s are remaining their 4-byte form, but now they might stay in a 2-byte alignment.An example:
Code is running at full speed on every hart. If this instruction is patched with unaligned access, the patching operation is not atomic anymore. In this respect, concurrency issues may occur, which are hard to address as
pc
s could fly to any place and the generated code seems to have no error.We solve this issue by using
ins_alignment(4)
to force the patchable jals to stay in a 4-byte aligned address.Jtreg tests
could reproduce this issue in small chances.
I have run these tests over nights to ensure the issue is solved. Also, other jtreg tests are passed.
Thanks,
Xiaolin