Releases: riscv-admin/riscv-ovpsim
Imperas Risc-V OVPsim Release v20200218.0
riscvOVPsim Change Log
Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model
Date 2020-February-19
Release 20200218.0
- Some Vector Extension issues have been corrected:
- Behavior of vmv.x.s and vfmv.f.s has been corrected when vstart>=vl so that
the result register is correctly updated (previously it was left unchanged
in this case). - Behavior of whole-register operations when vtype.vill=1 has been corrected
(these instructions should execute even when vtype.vill=1). - Behavior of vid.v has been corrected when vstart!=0.
- Behavior of vmv.x.s and vfmv.f.s has been corrected when vstart>=vl so that
Imperas Risc-V OVPsim Release v20200212.0
riscvOVPsim Change Log
Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model
NOTE: X-commit messages below refer to git commits in the following
Risc-V specification document repositories:
I-commit: https://github.com/riscv/riscv-isa-manual
V-commit: https://github.com/riscv/riscv-v-spec
Date 2020-February-13
Release 20200212.0
- Some details of CSR access behavior have been corrected:
- For Vector Extension version 0.8, access to vxsat and vxrm now requires both
mstatus.FS and mstatus.VS to be non-zero; previously, only non-zero
mstatus.FS was required. Note that from Vector Extension version 0.9
onwards, only mstatus.VS is required because these two fields are now
aliased in the new vcsr CSR instead of the fcsr CSR.
- For Vector Extension version 0.8, access to vxsat and vxrm now requires both
- An issue has been fixed in which an incorrect exception was raised on an
access error during a page table walk. - Some Vector Extension issues have been corrected:
- Behavior of vpopc.m and vfirst.m has been corrected when vl==0.
- Executing vsetvl/vsetvli instructions now sets vector state to dirty.
- Behavior of whole-register operations when vstart!=0 has been corrected.
- Vector indexed segment load instructions now raise an Illegal Instruction
if the destination vector register overlaps either source or mask. - Decodes for vqmaccus and vqmaccsu instructions have been exchanged to match
the specification - Implementations of vmv.s.x, vfmv.f.s and vfmv.s.f have been corrected to
prevent Illegal Instruction exceptions being reported for odd-numbered
vector registers for non-zero LMUL. These instructions should ignore LMUL. - Instruction vfmv.s.f has been corrected to validate that the argument is
NaN-boxed when required.
- The vector version master branch currently has these differences compared to
the previous 0.8 version:- V-commit bdb8b55: mstatus.VS and sstatus.VS fields have moved to bits 10:9;
- V-commit b25b643: new CSR vcsr has been added and fields VXSAT and VXRM
fields relocated there from CSR fcsr
Imperas Risc-V OVPsim Release v20200206.0
riscvOVPsim Change Log
Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model
NOTE: X-commit messages below refer to git commits in the following
Risc-V specification document repositories:
I-commit: https://github.com/riscv/riscv-isa-manual
V-commit: https://github.com/riscv/riscv-v-spec
Date 2020-February-06
Release 20200206.0
-
Bit Manipulation Extension
- Corrected sign extension for addwu, subwu, addiwu and slliu.w that were
incorrectly changed in the last fix.
- Corrected sign extension for addwu, subwu, addiwu and slliu.w that were
-
Command line argument 'memory' is modified so that permissions argument is required
and uses the characters rR, wW and xX for read, write and execute.