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Imperas Risc-V OVPsim Release v20200218.0
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@Imperas Imperas released this 21 May 20:01
· 30 commits to master since this release
v20200218.0
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riscvOVPsim Change Log

Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com

This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model

Date 2020-February-19
Release 20200218.0

  • Some Vector Extension issues have been corrected:
    • Behavior of vmv.x.s and vfmv.f.s has been corrected when vstart>=vl so that
      the result register is correctly updated (previously it was left unchanged
      in this case).
    • Behavior of whole-register operations when vtype.vill=1 has been corrected
      (these instructions should execute even when vtype.vill=1).
    • Behavior of vid.v has been corrected when vstart!=0.
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