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Imperas Risc-V OVPsim Release v20200616.0
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@Imperas Imperas released this 17 Jun 15:35
· 12 commits to master since this release
v20200616.0
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riscvOVPsim Change Log

Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com

This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model

Date 2020-Jun-16
Release 20200616.0

  • Core-Local Interrupt Controller (CLIC)
    • address for xintthresh CSRs have been changed to 0xm47 (previously 0xm4A)
  • Vector Extension
    • Checking of overlap of vector registers for vector indexed segment loads and
      stores has been corrected.
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