some general fixes. Addition of Vector v0.9 support : v20200518.0

ChangeLog.md

@@ -11,6 +11,45 @@ NOTE: X-commit messages below refer to git commits in the following
   I-commit: https://github.com/riscv/riscv-isa-manual
   V-commit: https://github.com/riscv/riscv-v-spec
 
+- EBREAK and ECALL no longer count as retired instructions if priv_version
+  is set to master.
+- SC instruction behavior has been changed so that store address alignment is
+  validated even if the reservation check fails (previously, alignment was
+  validated only if the reservation check succeeded).
+- Masking of the mcountinhibit CSR has been corrected - previously, bit 1 and
+  bits 63...32 were writeable when they should have been 0.
+- The nmi signal has been corrected to match the documented behavior, execution
+  resumes at the nmi_address parameter value when the nmi signal goes high
+- The optional Core-Local Interrupt Controller (CLIC) has been implemented
+  (version 0.9-draft-20191208).
+- Vector version 0.9 has been added, and is now used by default. Differences
+  compared to the previous 0.8 version are as follows (with the associated
+  specification V-commit identifiers):
+  - V-commit bdb8b55: mstatus.VS and sstatus.VS fields have moved to bits 10:9;
+  - V-commit b25b643: new CSR vcsr has been added and fields VXSAT and VXRM
+    fields relocated there from CSR fcsr;
+  - V-commit 951b64f: mirrors of fcsr fields have been removed from vcsr.
+  - V-commit 1aceea2: vfslide1up.vf and vfslide1down.vf instructions added.
+  - V-commit e256d65: vfcvt.rtz.xu.f.v, vfcvt.rtz.x.f.v, vfwcvt.rtz.xu.f.v,
+    vfwcvt.rtz.x.f.v, vfncvt.rtz.xu.f.v and vfncvt.rtz.x.f.v instructions added;
+  - V-commit 8a9fbce (and others): fractional LMUL support added, controlled by
+    an extended vtype.vlmul CSR field;
+  - V-commit f414f4d (and others): vector tail agnostic and vector mask agnostic
+    fields added to the vtype CSR;
+  - V-commit a526fb9 (and others): all vector load/store instructions replaced
+    with new instructions that explicitly encode EEW of data or index;
+  - V-commit ef531ea: whole register load and store operation encodings changed;
+  - V-commit bdc85cd: vzext.vf2, vsext.vf2, vzext.vf4, vsext.vf4, vzext.vf8 and
+     vsext.vf8 instructions added;
+  - V-commit 9a77e12: MLEN is always 1.
+- Some Vector Extension issues have been corrected:
+  - Instructions vfmv.s.f and vfmv.f.s now require that SEW is a supported
+    floating point size (pending vector specification clarification).
+
+Date 2020-March-31
+Release 20200330.0
+===
+
 - The priority order for handling simultaneous interrupts destined for the
   same privilege level has been corrected (previously, these were handled so
   that higher interrupt numbers were higher priority).

README.md

@@ -4,14 +4,14 @@ A Complete, Fully Functional, Configurable RISC-V Simulator
 ===
 
 Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 30 Mar 2020 
-Version: 20200330.0  
+Date   : 18 May 2020 
+Version: 20200518.0  
 License: Model source included under Apache 2.0 open source license  
 License: Simulator riscvOVPsim licensed under Open Virtual Platforms (OVP) Fixed Platform Kits license  
 RISC-V Specifications currently supported:
 - RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 20190305-Base-Ratification)
 - RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 20190405-Priv-MSU-Ratification)
-- RISC-V Instruction Set Manual, RISC-V "V" Vector Extension (with version configurable in the model using the 'vector_version' parameter. 'master' version conforms to specification changes up to 4 March 2020 and is regularly updated to track the evolving specification.)
+- RISC-V Instruction Set Manual, RISC-V "V" Vector Extension (with version configurable in the model using the 'vector_version' parameter. 'master' version conforms to specification changes up to 15 May 2020 and is regularly updated to track the evolving specification.)
 - RISCV Extension B (Bit Manipulation)
   - Run command: riscvOVPsim.exe --override riscvOVPsim/cpu/add_Extensions=B --showoverrides 
   - This will produce a formatted string, similar to 'Info (Bit Manipulation) extB Version(0.92) November 08 2019'

source/riscvAttrs.c

@@ -66,6 +66,7 @@ const vmiIASAttr modelAttrs = {
     // CONSTRUCTOR/DESTRUCTOR ROUTINES
     ////////////////////////////////////////////////////////////////////////
 
+    .smpNameCB          = riscvGetSMPName,
     .constructorCB      = riscvConstructor,
     .postConstructorCB  = riscvPostConstructor,
     .vmInitCB           = riscvVMInit,
@@ -79,6 +80,8 @@ const vmiIASAttr modelAttrs = {
     .endBlockCB         = riscvEndBlock,
     .morphCB            = riscvMorph,
     .fetchSnapCB        = riscvFetchSnap,
+    .rdSnapCB           = riscvRdSnap,
+    .wrSnapCB           = riscvWrSnap,
 
     ////////////////////////////////////////////////////////////////////////
     // SIMULATION SUPPORT ROUTINES
@@ -99,6 +102,8 @@ const vmiIASAttr modelAttrs = {
     .wrAlignExceptCB    = riscvWrAlignExcept,
     .rdAbortExceptCB    = riscvRdAbortExcept,
     .wrAbortExceptCB    = riscvWrAbortExcept,
+    .rdDeviceExceptCB   = riscvRdDeviceExcept,
+    .wrDeviceExceptCB   = riscvWrDeviceExcept,
     .ifetchExceptCB     = riscvIFetchExcept,
     .arithResultCB      = riscvArithResult,
 

source/riscvBlockState.h

@@ -39,15 +39,18 @@ typedef enum riscvSEWMtE {
 } riscvSEWMt;
 
 //
-// This indicates the known active vector length multiplier (VLMUL)
+// This indicates 8x the known active vector length multiplier (VLMUL)
 //
-typedef enum riscvVLMULMtE {
-    VLMULMT_UNKNOWN = 0,
-    VLMULMT_1       = 1,
-    VLMULMT_2       = 2,
-    VLMULMT_4       = 4,
-    VLMULMT_8       = 8,
-} riscvVLMULMt;
+typedef enum riscvVLMULx8MtE {
+    VLMULx8MT_UNKNOWN = 0,
+    VLMULx8MT_0125    = 1,
+    VLMULx8MT_025     = 2,
+    VLMULx8MT_05      = 4,
+    VLMULx8MT_1       = 8,
+    VLMULx8MT_2       = 16,
+    VLMULx8MT_4       = 32,
+    VLMULx8MT_8       = 64,
+} riscvVLMULx8Mt;
 
 //
 // This indicates the known active vector length zero/non-zero state
@@ -73,7 +76,7 @@ typedef enum riscvTZE {
 // and transaction mode
 //
 typedef enum riscvPMKE {
-    PMK_VECTOR      = 0x00ff,
+    PMK_VECTOR      = 0x03ff,
     PMK_TRANSACTION = 0x8000,
 } riscvPMK;
 
@@ -87,10 +90,33 @@ typedef struct riscvBlockStateS {
     Bool             FSDirty;       // is status.FS known to be dirty?
     Bool             VSDirty;       // is status.VS known to be dirty?
     riscvSEWMt       SEWMt;         // known active vector SEW
-    riscvVLMULMt     VLMULMt;       // known active vector VLMUL
+    riscvVLMULx8Mt   VLMULx8Mt;     // known active vector VLMULx8
     riscvVLClassMt   VLClassMt;     // known active vector VL zero/non-zero/max
     Uns32            VZeroTopMt[2]; // known vector registers with zero top
     Bool             VStartZeroMt;  // vstart known to be zero?
 
 } riscvBlockState;
 
+//
+// Convert vsew value to riscvSEWMt type
+//
+inline static riscvSEWMt vsewToSEW(Uns32 vsew) {
+    return 8<<vsew;
+}
+
+//
+// Convert signed vlmul value to riscvVLMULx8Mt type
+//
+inline static riscvVLMULx8Mt svlmulToVLMULx8(Int32 svlmul) {
+    return (svlmul==-4) ? VLMULx8MT_UNKNOWN : (1<<(svlmul+3));
+}
+
+//
+// Get riscvVLMULx8Mt for vtype
+//
+inline static riscvVLMULx8Mt vtypeToVLMULx8(riscvVType vtype) {
+    return svlmulToVLMULx8(getSignedVLMUL(vtype.vlmul, vtype.vlmulf));
+}
+
+
+

source/riscvCLICTypes.h

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#pragma once
+
+// VMI header files
+#include "vmi/vmiTypes.h"
+
+
+////////////////////////////////////////////////////////////////////////////////
+// REGISTER DEFINITIONS
+////////////////////////////////////////////////////////////////////////////////
+
+//
+// Use this to declare a register type name
+//
+#define CLIC_FIELDS(_N) riscvCLICFields_##_N
+
+//
+// Use this to declare a register type name
+//
+#define CLIC_REG_TYPE(_N) riscvCLIC_##_N
+
+//
+// Use this to declare a 32-bit CLIC register
+//
+#define CLIC_REG_STRUCT_DECL(_N) typedef union { \
+    Uns32           bits;     \
+    CLIC_FIELDS(_N) fields;   \
+} CLIC_REG_TYPE(_N)
+
+// -----------------------------------------------------------------------------
+// cliccfg      (offset 0x0000)
+// -----------------------------------------------------------------------------
+
+typedef struct {
+    Uns32 nvbits :  1;
+    Uns32 nlbits :  4;
+    Uns32 nmbits :  2;
+    Uns32 _u1    : 25;
+} CLIC_FIELDS(cliccfg);
+
+// define 32 bit type
+CLIC_REG_STRUCT_DECL(cliccfg);
+
+// -----------------------------------------------------------------------------
+// clicinfo     (offset 0x0004)
+// -----------------------------------------------------------------------------
+
+typedef struct {
+    Uns32 num_interrupt  : 13;
+    Uns32 version        :  8;
+    Uns32 CLICINTCTLBITS :  4;
+    Uns32 _u1            :  7;
+} CLIC_FIELDS(clicinfo);
+
+// define 32 bit type
+CLIC_REG_STRUCT_DECL(clicinfo);
+
+// -----------------------------------------------------------------------------
+// clicintattr  (offset 0x1002+4*i etc)
+// -----------------------------------------------------------------------------
+
+typedef struct {
+    Uns32 shv  : 1;
+    Uns32 trig : 2;
+    Uns32 _u1  : 3;
+    Uns32 mode : 2;
+} CLIC_FIELDS(clicintattr);
+
+// define 32 bit type
+CLIC_REG_STRUCT_DECL(clicintattr);
+
+//
+// Use this to define a CLIC register
+//
+#define CLIC_REG_DECL(_N)   CLIC_REG_TYPE(_N) _N
+