update supported ruby version

(refs: rggen/rggen#226)
rggen · Dec 30, 2024 · c382944 · c382944
1 parent ef722f0
commit c382944
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Showing 22 changed files with 62 additions and 102 deletions.
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -8,7 +8,7 @@ jobs:
 
     strategy:
       matrix:
-        ruby: ['3.3', '3.2', '3.1', '3.0']
+        ruby: ['3.4', '3.3', '3.2', '3.1']
         frozen_string_literal: ['yes', 'no']
 
     env:

diff --git a/lib/rggen/veryl/bit_field/type/custom.rb b/lib/rggen/veryl/bit_field/type/custom.rb
@@ -5,47 +5,39 @@
     build do
       if external_read_data?
         input :value_in, {
-          name: "i_#{full_name}",
-          width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       else
         output :value_out, {
-          name: "o_#{full_name}",
-          width: width, array_size: array_size
+          name: "o_#{full_name}", width:, array_size:
         }
       end
       if bit_field.hw_write?
         input :hw_write_enable, {
-          name: "i_#{full_name}_hw_write_enable",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size:
         }
         input :hw_write_data, {
-          name: "i_#{full_name}_hw_write_data",
-          width: width, array_size: array_size
+          name: "i_#{full_name}_hw_write_data", width:, array_size:
         }
       end
       if bit_field.hw_set?
         input :hw_set, {
-          name: "i_#{full_name}_hw_set",
-          width: width, array_size: array_size
+          name: "i_#{full_name}_hw_set", width:, array_size:
         }
       end
       if bit_field.hw_clear?
         input :hw_clear, {
-          name: "i_#{full_name}_hw_clear",
-          width: width, array_size: array_size
+          name: "i_#{full_name}_hw_clear", width:, array_size:
         }
       end
       if bit_field.write_trigger?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
       if bit_field.read_trigger?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.rb b/lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.rb
@@ -4,17 +4,14 @@
   veryl do
     build do
       input :set, {
-        name: "i_#{full_name}_set",
-        width: width, array_size: array_size
+        name: "i_#{full_name}_set", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked",
-          width: width, array_size: array_size
+          name: "o_#{full_name}_unmasked", width:, array_size:
         }
       end
     end

diff --git a/lib/rggen/veryl/bit_field/type/ro_rotrg.rb b/lib/rggen/veryl/bit_field/type/ro_rotrg.rb
@@ -5,14 +5,12 @@
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}",
-          width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rotrg?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/veryl/bit_field/type/rohw.rb b/lib/rggen/veryl/bit_field/type/rohw.rb
@@ -5,15 +5,14 @@
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/row0trg_row1trg.rb b/lib/rggen/veryl/bit_field/type/row0trg_row1trg.rb
@@ -5,13 +5,11 @@
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}",
-          width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       output :trigger, {
-        name: "o_#{full_name}_trigger",
-        width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/rowo_rowotrg.rb b/lib/rggen/veryl/bit_field/type/rowo_rowotrg.rb
@@ -4,23 +4,19 @@
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}",
-          width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rowotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.rb b/lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.rb
@@ -4,12 +4,10 @@
   veryl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear",
-        width: width, array_size: array_size
+        name: "i_#{full_name}_clear", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.rb b/lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.rb
@@ -4,17 +4,14 @@
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if rwtrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/veryl/bit_field/type/rwc.rb b/lib/rggen/veryl/bit_field/type/rwc.rb
@@ -5,13 +5,11 @@
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_clear", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/rwe_rwl.rb b/lib/rggen/veryl/bit_field/type/rwe_rwl.rb
@@ -5,13 +5,11 @@
     build do
       unless bit_field.reference?
         input :control, {
-          name: "i_#{full_name}_#{enable_or_lock}",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_#{enable_or_lock}", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/rwhw.rb b/lib/rggen/veryl/bit_field/type/rwhw.rb
@@ -5,17 +5,14 @@
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}",
-        width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/rws.rb b/lib/rggen/veryl/bit_field/type/rws.rb
@@ -5,13 +5,11 @@
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_set", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb b/lib/rggen/veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
@@ -6,8 +6,7 @@
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/w0t_w1t.rb b/lib/rggen/veryl/bit_field/type/w0t_w1t.rb
@@ -4,8 +4,7 @@
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/w0trg_w1trg.rb b/lib/rggen/veryl/bit_field/type/w0trg_w1trg.rb
@@ -4,8 +4,7 @@
   veryl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger",
-        width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.rb b/lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.rb
@@ -4,13 +4,11 @@
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if wotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/veryl/bit_field/type/wrc_wrs.rb b/lib/rggen/veryl/bit_field/type/wrc_wrs.rb
@@ -4,8 +4,7 @@
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/veryl/feature.rb b/lib/rggen/veryl/feature.rb
@@ -7,31 +7,31 @@ class Feature < SystemVerilog::Common::Feature
 
       private
 
-      def create_if_instance(_, attributes, &block)
-        InterfaceInstance.new(attributes, &block)
+      def create_if_instance(_, attributes, &)
+        InterfaceInstance.new(attributes, &)
       end
 
-      def create_port(direction, attributes, &block)
+      def create_port(direction, attributes, &)
         attributes =
-          { direction: direction }
+          { direction: }
             .merge(attributes)
-        DataObject.new(:port, attributes, &block)
+        DataObject.new(:port, attributes, &)
       end
 
-      def create_modport(_, attributes, &block)
-        Modport.new(attributes, &block)
+      def create_modport(_, attributes, &)
+        Modport.new(attributes, &)
       end
 
-      def create_param(_, attributes, &block)
-        DataObject.new(:param, attributes, &block)
+      def create_param(_, attributes, &)
+        DataObject.new(:param, attributes, &)
       end
 
-      def create_const(_, attributes, &block)
-        DataObject.new(:const, attributes, &block)
+      def create_const(_, attributes, &)
+        DataObject.new(:const, attributes, &)
       end
 
-      def create_var(_, attributes, &block)
-        DataObject.new(:var, attributes, &block)
+      def create_var(_, attributes, &)
+        DataObject.new(:var, attributes, &)
       end
 
       define_entity :input, :create_port, :port, -> { register_block }

diff --git a/lib/rggen/veryl/register_block/veryl_top.rb b/lib/rggen/veryl/register_block/veryl_top.rb
@@ -8,7 +8,7 @@
 
       interface :register_if, {
         name: 'register_if', interface_type: 'rggen::rggen_register_if',
-        param_values: param_values, array_size: [total_registers], variables: ['value']
+        param_values:, array_size: [total_registers], variables: ['value']
       }
     end