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Add translation start/end outcomes #506

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Add translation start/end outcomes #506

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6a7bab4
Add translation start/end outcomes
bauereiss Apr 16, 2024
c565693
Add Isabelle support for translation start/end outcomes
bauereiss Apr 22, 2024
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89 changes: 89 additions & 0 deletions lib/concurrency_interface/translation.sail
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Original file line number Diff line number Diff line change
@@ -0,0 +1,89 @@
/*==========================================================================*/
/* Sail */
/* */
/* Sail and the Sail architecture models here, comprising all files and */
/* directories except the ASL-derived Sail code in the aarch64 directory, */
/* are subject to the BSD two-clause licence below. */
/* */
/* The ASL derived parts of the ARMv8.3 specification in */
/* aarch64/no_vector and aarch64/full are copyright ARM Ltd. */
/* */
/* Copyright (c) 2013-2024 */
/* Kathyrn Gray */
/* Shaked Flur */
/* Stephen Kell */
/* Gabriel Kerneis */
/* Robert Norton-Wright */
/* Christopher Pulte */
/* Peter Sewell */
/* Alasdair Armstrong */
/* Brian Campbell */
/* Thomas Bauereiss */
/* Anthony Fox */
/* Jon French */
/* Dominic Mulligan */
/* Stephen Kell */
/* Mark Wassell */
/* Alastair Reid (Arm Ltd) */
/* */
/* All rights reserved. */
/* */
/* This work was partially supported by EPSRC grant EP/K008528/1 <a */
/* href="http://www.cl.cam.ac.uk/users/pes20/rems">REMS: Rigorous */
/* Engineering for Mainstream Systems</a>, an ARM iCASE award, EPSRC IAA */
/* KTF funding, and donations from Arm. This project has received */
/* funding from the European Research Council (ERC) under the European */
/* Union’s Horizon 2020 research and innovation programme (grant */
/* agreement No 789108, ELVER). */
/* */
/* This software was developed by SRI International and the University of */
/* Cambridge Computer Laboratory (Department of Computer Science and */
/* Technology) under DARPA/AFRL contracts FA8650-18-C-7809 ("CIFV") */
/* and FA8750-10-C-0237 ("CTSRD"). */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* 1. Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* 2. Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in */
/* the documentation and/or other materials provided with the */
/* distribution. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */
/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */
/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */
/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */
/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */
/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */
/* SUCH DAMAGE. */
/*==========================================================================*/

$sail_internal

$ifndef _CONCURRENCY_INTERFACE_TRANSLATION
$define _CONCURRENCY_INTERFACE_TRANSLATION

$include <concurrency_interface/common.sail>

outcome sail_translation_start : 'trans_start -> unit
with
'trans_start : Type
= {
impl emulator(_) = ()
}

outcome sail_translation_end : 'trans_end -> unit
with
'trans_end : Type
= {
impl emulator(_) = ()
}

$endif
8 changes: 8 additions & 0 deletions lib/isabelle/Sail2_concurrency_interface_lemmas.thy
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Expand Up @@ -40,6 +40,8 @@ inductive_set T (*:: "(('rv, 'a, 'e) monad \<times> 'rv event \<times> ('rv, 'a,
| Read_mem: "((Mem_read_request req k), E_mem_read_request req v, k v) \<in> T"
| Write_mem: "((Mem_write_request req k), E_mem_write_request req r, k r) \<in> T"
| Write_announce: "((Mem_write_announce_address a k), E_mem_write_announce_address a, k) \<in> T"
| Translation_start: "((Translation_start ts k), E_translation_start ts, k) \<in> T"
| Translation_end: "((Translation_end te k), E_translation_end te, k) \<in> T"
| Branch_announce: "((Branch_announce_address a k), E_branch_announce_address a, k) \<in> T"
| Barrier_request: "((Barrier_request r k), E_barrier_request r, k) \<in> T"
| Cache_op_request: "((Cache_op_request r k), E_cache_op_request r, k) \<in> T"
Expand All @@ -62,6 +64,8 @@ lemma emitEvent_cases:
| (Read_mem) req k v where "m = Mem_read_request req k" and "e = E_mem_read_request req v" and "m' = k v"
| (Write_mem) req k r where "m = Mem_write_request req k" and "e = E_mem_write_request req r" and "m' = k r"
| (Write_announce) a k where "m = Mem_write_announce_address a k" and "e = E_mem_write_announce_address a" and "m' = k"
| (Translation_start) ts k where "m = Translation_start ts k" and "e = E_translation_start ts" and "m' = k"
| (Translation_end) te k where "m = Translation_end te k" and "e = E_translation_end te" and "m' = k"
| (Branch_announce) a k where "m = Branch_announce_address a k" and "e = E_branch_announce_address a" and "m' = k"
| (Barrier_request) r k where "m = Barrier_request r k" and "e = E_barrier_request r" and "m' = k"
| (Cache_op_request) r k where "m = Cache_op_request r k" and "e = E_cache_op_request r" and "m' = k"
Expand Down Expand Up @@ -109,6 +113,8 @@ lemma Traces_cases:
| (Read_mem) req k t' v where "m = Mem_read_request req k" and "t = E_mem_read_request req v # t'" and "(k v, t', m') \<in> Traces"
| (Write_mem) req k v t' where "m = Mem_write_request req k" and "t = E_mem_write_request req v # t'" and "(k v, t', m') \<in> Traces"
| (Write_announce) a k t' where "m = Mem_write_announce_address a k" and "t = E_mem_write_announce_address a # t'" and "(k, t', m') \<in> Traces"
| (Translation_start) ts k t' where "m = Translation_start ts k" and "t = E_translation_start ts # t'" and "(k, t', m') \<in> Traces"
| (Translation_end) te k t' where "m = Translation_end te k" and "t = E_translation_end te # t'" and "(k, t', m') \<in> Traces"
| (Branch_announce) a k t' where "m = Branch_announce_address a k" and "t = E_branch_announce_address a # t'" and "(k, t', m') \<in> Traces"
| (Barrier) r k t' where "m = Barrier_request r k" and "t = E_barrier_request r # t'" and "(k, t', m') \<in> Traces"
| (Cache_op) r k t' where "m = Cache_op_request r k" and "t = E_cache_op_request r # t'" and "(k, t', m') \<in> Traces"
Expand All @@ -134,6 +140,8 @@ lemma Traces_iffs:
"\<And>req k t m'. (Mem_read_request req k, t, m') \<in> Traces \<longleftrightarrow> (t = [] \<and> m' = Mem_read_request req k \<or> (\<exists>a t'. t = E_mem_read_request req a # t' \<and> (k a, t', m') \<in> Traces))"
"\<And>req k t m'. (Mem_write_request req k, t, m') \<in> Traces \<longleftrightarrow> (t = [] \<and> m' = Mem_write_request req k \<or> (\<exists>a t'. t = E_mem_write_request req a # t' \<and> (k a, t', m') \<in> Traces))"
"\<And>a k t m'. (Mem_write_announce_address a k, t, m') \<in> Traces \<longleftrightarrow> (t = [] \<and> m' = Mem_write_announce_address a k \<or> (\<exists>t'. t = E_mem_write_announce_address a # t' \<and> (k, t', m') \<in> Traces))"
"\<And>ts k t m'. (Translation_start ts k, t, m') \<in> Traces \<longleftrightarrow> (t = [] \<and> m' = Translation_start ts k \<or> (\<exists>t'. t = E_translation_start ts # t' \<and> (k, t', m') \<in> Traces))"
"\<And>te k t m'. (Translation_end te k, t, m') \<in> Traces \<longleftrightarrow> (t = [] \<and> m' = Translation_end te k \<or> (\<exists>t'. t = E_translation_end te # t' \<and> (k, t', m') \<in> Traces))"
"\<And>a k t m'. (Branch_announce_address a k, t, m') \<in> Traces \<longleftrightarrow> (t = [] \<and> m' = Branch_announce_address a k \<or> (\<exists>t'. t = E_branch_announce_address a # t' \<and> (k, t', m') \<in> Traces))"
"\<And>req k t m'. (Barrier_request req k, t, m') \<in> Traces \<longleftrightarrow> (t = [] \<and> m' = Barrier_request req k \<or> (\<exists>t'. t = E_barrier_request req # t' \<and> (k, t', m') \<in> Traces))"
"\<And>req k t m'. (Cache_op_request req k, t, m') \<in> Traces \<longleftrightarrow> (t = [] \<and> m' = Cache_op_request req k \<or> (\<exists>t'. t = E_cache_op_request req # t' \<and> (k, t', m') \<in> Traces))"
Expand Down
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