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SV: Allow generating toplevel module with clk and reset signals #1503

SV: Allow generating toplevel module with clk and reset signals

SV: Allow generating toplevel module with clk and reset signals #1503

Triggered via push November 26, 2024 15:14
Status Success
Total duration 1m 17s
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formatting.yml

on: push
Matrix: build
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4 errors and 2 notices
725 tests found
There are 725 tests, see "Raw output" for the full list of tests.
725 tests found
There are 725 tests, see "Raw output" for the full list of tests.