feat: support aarch64 sel4test

src/arch/aarch64/arm_gic/gic_v2/consts.rs

@@ -1,10 +1,7 @@
-// the reg start physical addr of gic v2
-// but I don't know the virtual addr now
-// TODO
-pub const GIC_V2_PPTR: usize = 0x8000000;
-pub const GIC_V2_DISTRIBUTOR_PPTR: usize = GIC_V2_PPTR;
-pub const GIC_V2_CONTROLLER_PPTR: usize = GIC_V2_DISTRIBUTOR_PPTR + 0x10000;
-pub const GIC_V2_VCPUCTRL_PPTR: usize = GIC_V2_CONTROLLER_PPTR + 0x10000;
+// pub const GIC_V2_PPTR: usize = 0x8000000;
+pub const GIC_V2_PPTR: usize = 0xffffffffffe00000;
+pub const GIC_V2_DISTRIBUTOR_PPTR: usize = GIC_V2_PPTR + 0x1000;
+pub const GIC_V2_CONTROLLER_PPTR: usize = GIC_V2_PPTR + 0x2000;
 
 pub const IRQ_SET_ALL: u32 = 0xffffffff;
 pub const IRQ_MASK: u32 = (1 << (10)) - 1;

src/arch/aarch64/arm_gic/gic_v2/gic_v2.rs

@@ -32,3 +32,20 @@ pub fn cpu_iface_init() {
 pub fn cpu_initLocalIRQController() {
     cpu_iface_init();
 }
+
+/// Enable the IRQ controller
+pub fn irq_enable(irq: usize) {
+    let word = irq >> 5;
+    let bits = (irq & 0x1f) as u32;
+    GIC_DIST.regs().enable_set[word].set(1 << bits);
+}
+
+/// Get the current interrupt number
+pub fn gic_int_ack() -> usize {
+    GIC_CPUIFACE.regs().int_ack.get() as usize
+}
+
+/// Acknowledge the interrupt
+pub fn ack_irq(irq: usize) {
+    GIC_CPUIFACE.regs().eoi.set(irq as _);
+}

src/arch/aarch64/arm_gic/gic_v2/mod.rs

@@ -1,6 +1,7 @@
 pub mod consts;
 pub mod gic_v2;
 
+pub use gic_v2::irq_enable;
 use core::ptr::NonNull;
 use tock_registers::register_structs;
 use tock_registers::registers::{ReadOnly, ReadWrite, WriteOnly};

src/arch/aarch64/c_traps.rs

@@ -1,22 +1,12 @@
-use super::read_scause;
-use crate::{
-    config::{
-        RISCVInstructionAccessFault, RISCVInstructionPageFault, RISCVLoadAccessFault,
-        RISCVLoadPageFault, RISCVStoreAccessFault, RISCVStorePageFault,
-    },
-    syscall::slowpath,
-};
-
-use super::exception::{handleUserLevelFault, handleVMFaultEvent};
 use crate::interrupt::handler::handleInterruptEntry;
+use crate::syscall::slowpath;
 
 #[cfg(feature = "ENABLE_SMP")]
 use crate::{
     deps::{clh_is_self_in_queue, clh_lock_acquire, clh_lock_release},
     interrupt::getActiveIRQ,
 };
 
-use sel4_common::ffi_call;
 #[cfg(feature = "ENABLE_SMP")]
 use sel4_common::utils::cpu_id;
 use sel4_task::get_currenct_thread;
@@ -98,10 +88,12 @@ pub fn restore_user_context() {
 
 #[no_mangle]
 pub fn c_handle_interrupt() {
-    // debug!("c_handle_interrupt");
+    // log::debug!("c_handle_interrupt");
     // if hart_id() != 0 {
     //     debug!("c_handle_interrupt");
     // }
+    entry_hook();
+
     #[cfg(feature = "ENABLE_SMP")]
     {
         use crate::config::INTERRUPT_IPI_0;

src/arch/aarch64/exception.rs

@@ -1,11 +1,14 @@
-use super::read_stval;
+use crate::arch::aarch64::consts::ARMDataAbort;
 use crate::arch::aarch64::consts::ARMPrefetchAbort;
 use crate::kernel::boot::current_fault;
 use crate::syscall::handle_fault;
-use crate::{arch::aarch64::consts::ARMDataAbort, config::*};
+use aarch64_cpu::registers::Readable;
+use aarch64_cpu::registers::TTBR0_EL1;
+use sel4_common::arch::ArchReg;
 use sel4_common::fault::seL4_Fault_t;
 use sel4_common::structures::exception_t;
-use sel4_task::{activateThread, get_currenct_thread, schedule};
+use sel4_common::utils::global_read;
+use sel4_task::{activateThread, get_currenct_thread, get_current_domain, schedule};
 
 use super::instruction::*;
 
@@ -28,7 +31,6 @@ pub fn handleVMFaultEvent(vm_faultType: usize) -> exception_t {
     }
     schedule();
     activateThread();
-    log::debug!("active thread");
     exception_t::EXCEPTION_NONE
 }
 
@@ -54,11 +56,7 @@ pub fn handle_vm_fault(type_: usize) -> exception_t {
             word_t pc, fault;
             pc = getRestartPC(thread);
             fault = getIFSR();
-    #ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
-            if (ARCH_NODE_STATE(armHSVCPUActive)) {
-                pc = GET_PAR_ADDR(addressTranslateS1(pc)) | (pc & MASK(PAGE_BITS));
-            }
-    #endif
+
             current_fault = seL4_Fault_VMFault_new(pc, fault, true);
             return EXCEPTION_FAULT;
         }
@@ -69,17 +67,32 @@ pub fn handle_vm_fault(type_: usize) -> exception_t {
     */
     // ARMDataAbort = seL4_DataFault,               0
     // ARMPrefetchAbort = seL4_InstructionFault     1
-    log::debug!("Handle VM fault: {}", type_);
+    log::debug!(
+        "Handle VM fault: {}  domain: {}",
+        type_,
+        get_current_domain()
+    );
     match type_ {
         ARMDataAbort => {
             let addr = get_far();
             let fault = get_esr();
             log::debug!("fault addr: {:#x} esr: {:#x}", addr, fault);
-            seL4_Fault_t::new_vm_fault(addr, fault, 0);
+            unsafe {
+                current_fault = seL4_Fault_t::new_vm_fault(addr, fault, 0);
+            }
+            log::debug!("current_fault: {:#x?}", global_read!(current_fault));
             exception_t::EXCEPTION_FAULT
         }
         ARMPrefetchAbort => {
-            todo!("prefetch Abort");
+            let pc = get_currenct_thread().tcbArch.get_register(ArchReg::FaultIP);
+            let fault = get_esr();
+            unsafe {
+                current_fault = seL4_Fault_t::new_vm_fault(pc, fault, 1);
+            }
+
+            log::debug!("ttbr0_el1: {:#x?}", TTBR0_EL1.get());
+
+            log::debug!("fault pc: {:#x}  fault: {:#x}", pc, fault);
             exception_t::EXCEPTION_FAULT
         }
         _ => panic!("Invalid VM fault type:{}", type_),

src/arch/aarch64/mod.rs

@@ -9,20 +9,11 @@ mod platform;
 
 pub mod arm_gic;
 
-use crate::config::RESET_CYCLES;
+use aarch64_cpu::registers::{Writeable, CNTV_CTL_EL0, CNTV_TVAL_EL0};
 pub use boot::try_init_kernel;
 pub use c_traps::restore_user_context;
+pub(crate) use pg::set_vm_root_for_flush;
 pub use platform::init_freemem;
-use sel4_common::arch::set_timer;
-
-pub fn read_stval() -> usize {
-    // let temp: usize;
-    // unsafe {
-    //     asm!("csrr {}, stval",out(reg)temp);
-    // }
-    // temp
-    todo!("read_stval")
-}
 
 pub fn read_sip() -> usize {
     // let temp: usize;
@@ -33,30 +24,15 @@ pub fn read_sip() -> usize {
     todo!("read_sip")
 }
 
-pub fn read_time() -> usize {
-    // let temp: usize;
-    // unsafe {
-    //     asm!("rdtime {}",out(reg)temp);
-    // }
-    // temp
-    todo!("read_time")
-}
-
-pub fn read_scause() -> usize {
-    // let temp: usize;
-    // unsafe {
-    //     asm!("csrr {}, scause",out(reg)temp);
-    // }
-    // temp
-    todo!("read_scause")
-}
-
+/// Reset the current Timer
 #[no_mangle]
 pub fn resetTimer() {
-    let mut target = read_time() + RESET_CYCLES;
-    set_timer(target);
-    while read_time() > target {
-        target = read_time() + RESET_CYCLES;
-        set_timer(target);
-    }
+    /*
+        SYSTEM_WRITE_WORD(CNT_TVAL, TIMER_RELOAD);
+        SYSTEM_WRITE_WORD(CNT_CTL, BIT(0));
+    */
+    const TIMER_CLOCK_HZ: u64 = 62500000;
+    // TODO: Set a proper timer clock
+    CNTV_TVAL_EL0.set(TIMER_CLOCK_HZ / 1000 * 10);
+    CNTV_CTL_EL0.set(1);
 }

src/arch/aarch64/pg.rs

@@ -1,8 +1,13 @@
 use crate::syscall::invocation::decode::arch::decode_mmu_invocation;
 use sel4_common::arch::MessageLabel;
+use sel4_common::sel4_config::tcbVTable;
 use sel4_common::structures::exception_t;
 use sel4_common::structures::seL4_IPCBuffer;
 use sel4_cspace::interface::{cap_t, cte_t};
+use sel4_task::get_currenct_thread;
+use sel4_vspace::asid_t;
+use sel4_vspace::setCurrentUserVSpaceRoot;
+use sel4_vspace::ttbr_new;
 use sel4_vspace::{vptr_t, PTE};
 
 #[repr(C)]
@@ -24,21 +29,21 @@ struct lookupPUDSlot_ret_t {
 }
 
 #[no_mangle]
-extern "C" fn lookupPGDSlot(vspace: *mut PTE, vptr: vptr_t) -> lookupPGDSlot_ret_t {
+extern "C" fn lookupPGDSlot(_vspace: *mut PTE, _vptr: vptr_t) -> lookupPGDSlot_ret_t {
     // which is realized under sel4_vspace/src/arch/aarch64/pte.rs as a member function of PTE in this commit
     // ZhiyuanSue
     todo!("lookupPGDSlot")
 }
 
 #[no_mangle]
-extern "C" fn lookupPDSlot(vspace: *mut PTE, vptr: vptr_t) -> lookupPDSlot_ret_t {
+extern "C" fn lookupPDSlot(_vspace: *mut PTE, _vptr: vptr_t) -> lookupPDSlot_ret_t {
     // which is realized under sel4_vspace/src/arch/aarch64/pte.rs as a member function of PTE in this commit
     // ZhiyuanSue
     todo!("lookupPDSlot")
 }
 
 #[no_mangle]
-extern "C" fn lookupPUDSlot(vspace: *mut PTE, vptr: vptr_t) -> lookupPUDSlot_ret_t {
+extern "C" fn lookupPUDSlot(_vspace: *mut PTE, _vptr: vptr_t) -> lookupPUDSlot_ret_t {
     // which is realized under sel4_vspace/src/arch/aarch64/pte.rs as a member function of PTE in this commit
     // ZhiyuanSue
     todo!("lookupPUDSlot")
@@ -49,12 +54,23 @@ extern "C" fn lookupPUDSlot(vspace: *mut PTE, vptr: vptr_t) -> lookupPUDSlot_ret
 extern "C" fn decodeARMMMUInvocation(
     invLabel: MessageLabel,
     length: usize,
-    cptr: usize,
+    _cptr: usize,
     cte: &mut cte_t,
-    cap: cap_t,
+    _cap: cap_t,
     call: bool,
     buffer: Option<&seL4_IPCBuffer>,
 ) -> exception_t {
-    // todo!("decodeARMMMUInvocation")
     decode_mmu_invocation(invLabel, length, cte, call, buffer)
 }
+
+/// Set VMRoot and flush if necessary
+pub fn set_vm_root_for_flush(vspace: usize, asid: asid_t) -> bool {
+    let thread_root = get_currenct_thread().get_cspace(tcbVTable).cap;
+
+    if thread_root.is_valid_native_root() && thread_root.get_pgd_base_ptr() == vspace as usize {
+        return false;
+    }
+
+    setCurrentUserVSpaceRoot(ttbr_new(asid, vspace));
+    true
+}

src/arch/riscv/exception.rs

@@ -21,7 +21,6 @@ pub fn handleUserLevelFault(w_a: usize, w_b: usize) -> exception_t {
 pub fn handleVMFaultEvent(vm_faultType: usize) -> exception_t {
     let status = handle_vm_fault(vm_faultType);
     if status != exception_t::EXCEPTION_NONE {
-        // debug!("handle_fault: {}", vm_faultType);
         handle_fault(get_currenct_thread());
     }
     schedule();

src/boot/root_server.rs

@@ -9,12 +9,14 @@ use crate::structures::{
 use crate::{BIT, ROUND_DOWN};
 use log::debug;
 use sel4_common::arch::{ArchReg, ArchTCB};
+#[cfg(target_arch = "riscv64")]
+use sel4_common::sel4_config::CONFIG_PT_LEVELS;
 #[cfg(target_arch = "aarch64")]
 use sel4_common::sel4_config::PT_INDEX_BITS;
 use sel4_common::sel4_config::{
     asidLowBits, seL4_PageBits, seL4_PageTableBits, seL4_SlotBits, seL4_TCBBits, tcbBuffer,
-    tcbCTable, tcbVTable, wordBits, CONFIG_MAX_NUM_NODES, CONFIG_NUM_DOMAINS, CONFIG_PT_LEVELS,
-    CONFIG_TIME_SLICE, IT_ASID, PAGE_BITS, TCB_OFFSET,
+    tcbCTable, tcbVTable, wordBits, CONFIG_MAX_NUM_NODES, CONFIG_NUM_DOMAINS, CONFIG_TIME_SLICE,
+    IT_ASID, PAGE_BITS, TCB_OFFSET,
 };
 use sel4_common::structures::{exception_t, seL4_IPCBuffer};
 use sel4_common::utils::convert_to_mut_type_ref;
@@ -66,8 +68,6 @@ pub fn root_server_init(
     }
 
     create_domain_cap(&root_cnode_cap);
-    //TODO: Implemente it for aarch64 in the future
-    #[cfg(target_arch = "riscv64")]
     init_irqs(&root_cnode_cap);
     unsafe {
         rust_populate_bi_frame(0, CONFIG_MAX_NUM_NODES, ipcbuf_vptr, extra_bi_size);
@@ -202,7 +202,6 @@ fn asid_init(root_cnode_cap: cap_t, it_pd_cap: cap_t) -> bool {
     }
     #[cfg(target_arch = "aarch64")]
     {
-
         write_it_asid_pool(&it_ap_cap, &it_pd_cap);
     }
     true

src/config.rs

@@ -109,11 +109,18 @@ pub const INTERRUPT_IPI_1: usize = 2;
 #[cfg(feature = "ENABLE_SMP")]
 pub const KERNEL_TIMER_IRQ: usize = 3;
 
-#[cfg(not(feature = "ENABLE_SMP"))]
+#[cfg(all(not(feature = "ENABLE_SMP"), target_arch = "riscv64"))]
 pub const KERNEL_TIMER_IRQ: usize = 1;
 
+#[cfg(all(not(feature = "ENABLE_SMP"), target_arch = "aarch64"))]
+pub const KERNEL_TIMER_IRQ: usize = 27;
+
+#[cfg(target_arch = "riscv64")]
 pub const maxIRQ: usize = KERNEL_TIMER_IRQ;
 
+#[cfg(target_arch = "aarch64")]
+pub const maxIRQ: usize = 159;
+
 pub const irqInvalid: usize = 0;
 
 pub const SEL4_BOOTINFO_HEADER_FDT: usize = 6;