Merge remote-tracking branch 'origin/mi_dev_zy' into mi_dev

.cargo/config.toml

@@ -5,9 +5,9 @@
 #
 
 [build]
-# target = "riscv64imac-unknown-none-elf"
+target = "riscv64imac-unknown-none-elf"
 # target = "riscv64imac-sel4"
-target = "aarch64-unknown-none-softfloat"
+# target = "aarch64-unknown-none-softfloat"
 
 [unstable]
 unstable-options = true

Cargo.toml

@@ -23,7 +23,9 @@ members = [
 [dependencies]
 buddy_system_allocator = "0.6"
 riscv = { git = "https://gitee.com/rcore-os/riscv", features = ["inline-asm"] }
+aarch64-cpu = "9.4.0"
 log = "0.4"
+tock-registers = "0.8"
 spin = { version = "0.9", features = ["use_ticket_mutex"] }
 sel4_common = { path = "./sel4_common" }
 sel4_cspace = { path = "./sel4_cspace" }

sel4_common/Cargo.toml

@@ -9,4 +9,4 @@ log = "0.4.21"
 spin = { version = "0.9", features = ["use_ticket_mutex"] }
 
 [features]
-ENABLE_SMP = []
+ENABLE_SMP = []

sel4_common/src/smp.rs

@@ -26,6 +26,7 @@ pub fn hart_id_to_core_id(hart_id: usize) -> usize {
 
 #[inline]
 pub fn get_currenct_cpu_index() -> usize {
+    #[cfg(target_arch = "riscv64")]
     unsafe {
         let mut cur_sp: usize;
         asm!(
@@ -35,6 +36,15 @@ pub fn get_currenct_cpu_index() -> usize {
         cur_sp -= kernel_stack_alloc as usize + 8;
         cur_sp >> CONFIG_KERNEL_STACK_BITS
     }
+    #[cfg(target_arch = "aarch64")]
+    unsafe {
+        let mut id: usize;
+        asm!(
+            "mrs {},tpidr_el1",
+            out(reg) id,
+        );
+        id & 0xfff
+    }
 }
 
 #[inline]

sel4_vspace/src/asid.rs

@@ -1,3 +1,4 @@
+#[cfg(target_arch = "riscv64")]
 use core::arch::asm;
 use core::intrinsics::unlikely;
 

sel4_vspace/src/satp.rs

@@ -1,7 +1,7 @@
 use super::structures::paddr_t;
 use riscv::register::satp;
 #[cfg(feature = "ENABLE_SMP")]
-use sel4_common::sbi::remote_sfence_vma;
+use sel4_common::arch::remote_sfence_vma;
 
 #[repr(C)]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]

src/arch/aarch64/arm_gic/gic_v2/consts.rs

@@ -0,0 +1,11 @@
+// the reg start physical addr of gic v2
+// but I don't know the virtual addr now
+// TODO
+pub const GIC_V2_PPTR: usize = 0x8000000;
+pub const GIC_V2_DISTRIBUTOR_PPTR: usize = GIC_V2_PPTR;
+pub const GIC_V2_CONTROLLER_PPTR: usize = GIC_V2_DISTRIBUTOR_PPTR + 0x10000;
+pub const GIC_V2_VCPUCTRL_PPTR: usize = GIC_V2_CONTROLLER_PPTR + 0x10000;
+
+pub const IRQ_SET_ALL: u32 = 0xffffffff;
+pub const IRQ_MASK: u32 = (1 << (10)) - 1;
+pub const IRQ_NONE: u32 = 1023;

src/arch/aarch64/arm_gic/gic_v2/gic_v2.rs

@@ -0,0 +1,34 @@
+use super::consts::*;
+use super::{Gic_Cpu_Iface_Map, Gic_Dist_Map};
+use aarch64_cpu::registers::Readable;
+use tock_registers::interfaces::Writeable;
+
+static GIC_DIST: Gic_Dist_Map = Gic_Dist_Map::new(GIC_V2_DISTRIBUTOR_PPTR as *mut u8);
+static GIC_CPUIFACE: Gic_Cpu_Iface_Map = Gic_Cpu_Iface_Map::new(GIC_V2_CONTROLLER_PPTR as *mut u8);
+// This is for aarch64 only
+pub fn cpu_iface_init() {
+    GIC_DIST.regs().enable_clr[0].set(IRQ_SET_ALL);
+    GIC_DIST.regs().pending_clr[0].set(IRQ_SET_ALL);
+    GIC_DIST.regs().security[0].set(0);
+    GIC_DIST.regs().priority[0].set(0x0);
+
+    let mut i = 0;
+    while i < 16 {
+        GIC_DIST.regs().sgi_pending_clr[i >> 2].set(IRQ_SET_ALL);
+        i += 4;
+    }
+
+    GIC_CPUIFACE.regs().icontrol.set(0);
+    GIC_CPUIFACE.regs().pri_msk_c.set(0);
+    GIC_CPUIFACE.regs().pb_c.set(0);
+    let mut i = GIC_CPUIFACE.regs().int_ack.get();
+    while (i & IRQ_MASK) != IRQ_NONE {
+        GIC_CPUIFACE.regs().eoi.set(0);
+        i = GIC_CPUIFACE.regs().int_ack.get();
+    }
+    GIC_CPUIFACE.regs().icontrol.set(1);
+}
+
+pub fn cpu_initLocalIRQController() {
+    cpu_iface_init();
+}

src/arch/aarch64/arm_gic/gic_v2/mod.rs

@@ -0,0 +1,125 @@
+pub mod consts;
+pub mod gic_v2;
+
+use core::ptr::NonNull;
+use tock_registers::register_structs;
+use tock_registers::registers::{ReadOnly, ReadWrite, WriteOnly};
+
+register_structs! {
+    /// GIC Distributor registers.
+    #[allow(non_snake_case)]
+    pub Gic_Dist_Map_Regs{
+        (0x000 => enable:ReadWrite<u32>),
+        (0x0004 => ic_type: ReadOnly<u32>),
+        (0x0008 => dist_ident: ReadOnly<u32>),
+        (0x000c => _reserved_1),
+        (0x0080 => security: [ReadWrite<u32>; 0x20]),
+        (0x0100 => enable_set: [ReadWrite<u32>; 0x20]),
+        (0x0180 => enable_clr: [ReadWrite<u32>; 0x20]),
+        (0x0200 => pending_set: [ReadWrite<u32>; 0x20]),
+        (0x0280 => pending_clr: [ReadWrite<u32>; 0x20]),
+        (0x0300 => active: [ReadWrite<u32>; 0x20]),
+        (0x0380 => res2: [ReadWrite<u32>; 0x20]),
+        (0x0400 => priority: [ReadWrite<u32>; 0xff]),
+        (0x07fC => _reserved_3),
+        (0x0800 => targets: [ReadWrite<u32>; 0xff]),
+        (0x0bfc => _reserved_4),
+        (0x0c00 => config: [ReadWrite<u32>; 0x40]),
+        (0x0d00 => spi: [ReadWrite<u32>; 0x20]),
+        (0x0d80 => _reserved_5),
+        (0x0dd4 => legacy_int: ReadWrite<u32>),
+        (0x0dd8 => _reserved_7),
+        (0x0de0 => match_d: ReadWrite<u32>),
+        (0x0de4 => enable_d: ReadWrite<u32>),
+        (0x0de8 => _reserved_8),
+        (0x0f00 => sgi_control: WriteOnly<u32>),
+        (0x0f04 => _reserved_9),
+        (0x0f10 => sgi_pending_clr: [ReadWrite<u32>; 0x4]),
+        (0x0f20 => _reserved_10),
+        (0x0fc0 => periph_id: [ReadWrite<u32>; 12]),
+        (0x0ff0 => component_id: [ReadWrite<u32>; 0x4]),
+        (0x1000 => @END),
+    }
+}
+
+register_structs! {
+    /// GIC CPU Interface registers.
+    #[allow(non_snake_case)]
+    pub Gic_Cpu_Iface_Map_Regs {
+        (0x0000 => icontrol: ReadWrite<u32>),
+        (0x0004 => pri_msk_c: ReadWrite<u32>),
+        (0x0008 => pb_c: ReadWrite<u32>),
+        (0x000c => int_ack: ReadOnly<u32>),
+        (0x0010 => eoi: WriteOnly<u32>),
+        (0x0014 => run_priority: ReadOnly<u32>),
+        (0x0018 => hi_pend: ReadOnly<u32>),
+        (0x001c => ns_alias_bp_c: ReadWrite<u32>),
+
+        (0x0020 => ns_alias_ack: ReadWrite<u32>),
+        (0x0024 => ns_alias_eoi: ReadWrite<u32>),
+        (0x0028 => ns_alias_hi_pend: ReadWrite<u32>),
+        (0x002c => _reserved_1),
+
+        (0x0040 => integ_en_c: ReadWrite<u32>),
+        (0x0044 => interrupt_out: ReadWrite<u32>),
+        (0x0048 => _reserved_2),
+
+        (0x0050 => match_c: ReadWrite<u32>),
+        (0x0054 => enable_c: ReadWrite<u32>),
+        (0x0058 => _reserved_3),
+
+        (0x00D0 => active_priority: [ReadWrite<u32>; 0x4]),
+        (0x00E0 => ns_active_priority: [ReadWrite<u32>; 0x4]),
+
+        (0x00f0 => _reserved_4),
+
+        (0x00fc => cpu_if_ident: ReadOnly<u32>),
+        (0x0100 => _reserved_5),
+
+        (0x0fc0 => periph_id: [ReadWrite<u32>; 0x8]),	//PL390 only
+        (0x0fe0 => _reserved_6),
+        (0x0ff0 => component_id: [ReadWrite<u32>; 0x4]),	//PL390 only
+        /// Deactivate Interrupt Register.
+        (0x1000 => @END),
+    }
+}
+
+pub struct Gic_Dist_Map {
+    base: NonNull<Gic_Dist_Map_Regs>,
+}
+
+pub struct Gic_Cpu_Iface_Map {
+    base: NonNull<Gic_Cpu_Iface_Map_Regs>,
+}
+
+unsafe impl Send for Gic_Dist_Map {}
+unsafe impl Sync for Gic_Dist_Map {}
+
+unsafe impl Send for Gic_Cpu_Iface_Map {}
+unsafe impl Sync for Gic_Cpu_Iface_Map {}
+
+impl Gic_Dist_Map {
+    /// Construct a new GIC distributor instance from the base address.
+    pub const fn new(base: *mut u8) -> Self {
+        Self {
+            base: NonNull::new(base).unwrap().cast(),
+        }
+    }
+
+    pub const fn regs(&self) -> &Gic_Dist_Map_Regs {
+        unsafe { self.base.as_ref() }
+    }
+}
+
+impl Gic_Cpu_Iface_Map {
+    /// Construct a new GIC CPU interface instance from the base address.
+    pub const fn new(base: *mut u8) -> Self {
+        Self {
+            base: NonNull::new(base).unwrap().cast(),
+        }
+    }
+
+    pub const fn regs(&self) -> &Gic_Cpu_Iface_Map_Regs {
+        unsafe { self.base.as_ref() }
+    }
+}

src/arch/aarch64/arm_gic/gic_v3/consts.rs

@@ -0,0 +1 @@
+

src/arch/aarch64/arm_gic/gic_v3/gic_v3.rs

@@ -0,0 +1 @@
+

src/arch/aarch64/arm_gic/gic_v3/mod.rs

@@ -0,0 +1,2 @@
+pub mod consts;
+pub mod gic_v3;

src/arch/aarch64/arm_gic/mod.rs

@@ -0,0 +1,2 @@
+pub mod gic_v2;
+pub mod gic_v3;

src/arch/aarch64/c_traps.rs

@@ -1,5 +1,3 @@
-use core::arch::asm;
-
 use super::read_scause;
 use crate::{
     config::{
@@ -27,7 +25,7 @@ use sel4_common::utils::cpu_id;
 pub fn restore_user_context() {
     unsafe {
         // debug!("restore_user_context");
-        let cur_thread_reg: usize = get_currenct_thread().tcbArch.registers.as_ptr() as usize;
+        let _cur_thread_reg: usize = get_currenct_thread().tcbArch.registers.as_ptr() as usize;
         #[cfg(feature = "ENABLE_SMP")]
         {
             if clh_is_self_in_queue() {
@@ -89,7 +87,7 @@ pub fn restore_user_context() {
         // "ld  t1, (5*8)(t0) \n",
         // "ld  t0, (4*8)(t0) \n",
         // "sret");
-        panic!("unreachable")
+        // panic!("unreachable")
     }
 }
 

src/arch/aarch64/ffi.rs

@@ -0,0 +1,4 @@
+extern "C" {
+    pub fn arm_vector_table();
+    pub fn initTimer();
+}

src/arch/aarch64/mod.rs

@@ -1,10 +1,13 @@
 mod c_traps;
 mod exception;
+mod ffi;
+mod platform;
 
-use core::arch::asm;
+pub mod arm_gic;
 
 use crate::config::RESET_CYCLES;
 pub use c_traps::restore_user_context;
+pub use platform::init_cpu;
 use sel4_common::arch::set_timer;
 
 pub fn read_stval() -> usize {
@@ -16,7 +19,7 @@ pub fn read_stval() -> usize {
     todo!("read_stval")
 }
 
-pub extern "C" fn write_stvec(val: usize) {
+pub extern "C" fn write_stvec(_val: usize) {
     // unsafe {
     //     asm!("csrw stvec , {}",in(reg) val);
     // }

src/arch/aarch64/platform.rs

@@ -0,0 +1,39 @@
+use aarch64_cpu::registers::Writeable;
+use aarch64_cpu::registers::{TPIDR_EL1, VBAR_EL1};
+use core::arch::asm;
+use sel4_common::sel4_config::CONFIG_KERNEL_STACK_BITS;
+use sel4_common::utils::cpu_id;
+
+use super::ffi::*;
+use crate::ffi::*;
+
+use super::arm_gic::gic_v2::gic_v2::cpu_initLocalIRQController;
+pub fn init_cpu() -> bool {
+    // use arch::aarch64::arm_gic::gic_v2;
+
+    // Setup kernel stack pointer.
+
+    // Wrapping_add, first argument is CURRENT_CPU_INDEX
+    //
+    let mut stack_top =
+        (kernel_stack_alloc as *mut u8).wrapping_add(0 + (1 << CONFIG_KERNEL_STACK_BITS)) as u64;
+    stack_top |= cpu_id() as u64; //the judge of enable smp have done in cpu_id
+
+    TPIDR_EL1.set(stack_top);
+    // CPU's exception vector table
+    unsafe {
+        asm!("dsb sy;"); // DSB SY
+        VBAR_EL1.set(arm_vector_table as u64);
+        asm!("isb;"); // ISB SY
+    }
+    // initLocalIRQController
+    cpu_initLocalIRQController();
+    // armv_init_user_access
+    // user_access::armv_init_user_access();
+    //initTimer
+
+    unsafe {
+        initTimer();
+    }
+    true
+}

src/arch/riscv/mod.rs

@@ -1,10 +1,12 @@
 mod c_traps;
 mod exception;
+mod platform;
 
+pub use c_traps::restore_user_context;
 use core::arch::asm;
+pub use platform::init_cpu;
 
 use crate::config::RESET_CYCLES;
-pub use c_traps::restore_user_context;
 use sel4_common::arch::sbi::set_timer;
 
 core::arch::global_asm!(include_str!("restore_fp.S"));

src/arch/riscv/platform.rs

@@ -0,0 +1,30 @@
+use riscv::register::{stvec, utvec::TrapMode};
+use sel4_common::{
+    arch::{get_time, set_timer},
+    BIT,
+};
+use sel4_vspace::activate_kernel_vspace;
+
+use crate::{
+    config::{RESET_CYCLES, SIE_SEIE, SIE_STIE},
+    interrupt::set_sie_mask,
+};
+
+pub fn init_cpu() {
+    activate_kernel_vspace();
+    extern "C" {
+        fn trap_entry();
+    }
+    unsafe {
+        stvec::write(trap_entry as usize, TrapMode::Direct);
+    }
+    #[cfg(feature = "ENABLE_SMP")]
+    {
+        set_sie_mask(BIT!(SIE_SEIE) | BIT!(SIE_STIE) | BIT!(SIE_SSIE));
+    }
+    #[cfg(not(feature = "ENABLE_SMP"))]
+    {
+        set_sie_mask(BIT!(SIE_SEIE) | BIT!(SIE_STIE));
+    }
+    set_timer(get_time() + RESET_CYCLES);
+}