fix read CE

cic.py

@@ -37,6 +37,8 @@ def __init__(self, width=16, rate_width=16, order=3, channels=4):
         # Thus to ensure overall gain of 1 choose rates that are powers
         # of two.
         self.shift = Signal(max=order*rate_width + 1)
+        # clock enable, drive together with a sync clock domain CE
+        self.cce = Signal(reset=1)
 
         ## Outputs
         # current input channel index
@@ -102,14 +104,15 @@ def __init__(self, width=16, rate_width=16, order=3, channels=4):
         we = Signal(len(layout), reset_less=True, reset=(1 << len(layout)) - 1)
 
         mem = Memory(len(read), channels)
-        mem_r = mem.get_port()
+        mem_r = mem.get_port(has_re=True)
         mem_w = mem.get_port(write_capable=True, we_granularity=1)
         self.specials += mem, mem_r, mem_w
         self.comb += [
             read.raw_bits().eq(mem_r.dat_r),
             mem_w.dat_w.eq(write.raw_bits()),
             mem_r.adr.eq(mem_w.adr + 2),  # TODO: modulo if not power of two
             mem_w.adr.eq(channel),
+            mem_r.re.eq(self.cce),
             mem_w.we.eq(Cat(
                 Replicate(we[i], len(sig))
                 for i, (sig, _) in enumerate(write.iter_flat()))),

fastino_phy.py

@@ -168,7 +168,7 @@ def __init__(self, platform):
                 self.int0.x,
                 self.int1.x,
         )
-        self.sync.spi += [
+        self.sync.spi += [  # this should be comb but the stb path is long
             self.int0.stb_in.eq(self.frame.stb),
             self.int1.stb_in.eq(self.frame.stb),
             body.eq(self.frame.body[-len(body):]),

interpolator.py

@@ -35,6 +35,7 @@ def __init__(self, n_channels=16, n_bits=16, n_mantissa=6, n_exp=4,
             cic.shift.eq(sr[0][n_mantissa + n_exp:]),
             Cat(self.y).eq(Cat(sr[-n_channels:])),
             self.en_out.eq(enable[-n_channels:]),
+            cic.cce.eq(cic.ce),
         ]
         self.sync += [
             If(cic.ce,